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/rk3399_rockchip-uboot/doc/
H A DREADME.fsl-esdhc18 ESDHC IP is in little-endian mode. Accessing ESDHC registers can be
19 determined by ESDHC IP's endian mode or processor's endian mode.
21 ESDHC IP is in big-endian mode. Accessing ESDHC registers can be determined
22 by ESDHC IP's endian mode or processor's endian mode.
H A DREADME.SNTP6 parameter of server's IP address or environment variable
11 If the DHCP server provides time server's IP or time offset, you
16 2. Only the 1st NTP server IP, in the option ntp-servers of DHCP, will
H A DREADME.NetConsole11 We use an environment variable 'ncip' to set the IP address and the
14 broadcast address and port 6666 are used. If it is set to an IP
20 For example, if your server IP is 192.168.1.1, you could use:
33 specify the target IP address (or host name, assuming DNS is working). The
49 Minimally, the host IP address needs to be specified. This can be
65 src-ip source IP to use
71 tgt-ip IP address for logging agent
87 the respective Ethernet interface has to be brought up using the "IP
H A DREADME.mxc_ocotp4 This IP can be found on the following SoCs:
8 Note that this IP is different from albeit similar to the IPs of the same name
H A DREADME.fuse14 fusebox control IP registers. This is limited to 32 bits with the current API.
19 Upon startup, the fusebox control IP reads the fuse values and stores them to a
43 each IP.
H A DREADME.dns11 Internet by translating human-friendly computer hostnames into IP addresses.
31 By default, dns does nothing except print the IP number on
H A DREADME.odroid183 Automatic IP assignment:
197 Note that this automatically sets the many IP address related variables in
215 Static IP assignment:
218 set the IP address statically, it can be done by:
236 TFTP from server 192.168.1.27; our IP address is 192.168.1.10
249 TFTP from server 192.168.1.27; our IP address is 192.168.1.10
H A DREADME.usb72 to obtain an IP address and load a kernel from a network server.
151 gateway IP, host name and boot path from the bootp/dhcp server. These
159 You can also set the default IP address of your board and the server
185 Then 'bootp' or 'dhcp' should use it to obtain an IP address from DHCP,
194 TFTP from server 172.22.72.144; our IP address is 172.22.73.81
H A DREADME.ARC6 http://www.synopsys.com/IP/ProcessorIP/ARCProcessors/Pages/default.aspx
H A DREADME.fsl_iim3 This IP can be found on the following SoCs:
H A DREADME.link-local2 Link-local IP address auto-configuration
H A DREADME.socfpga28 projects must have the IP cores updated as shown below.
42 Then (if necessary) update the IP cores in the project, generate HDL code, and
/rk3399_rockchip-uboot/drivers/spi/
H A DKconfig33 IP core. Please find details on the "Embedded Peripherals IP
41 this Andestech IP core.
88 Cadence IP core.
95 IP core.
102 Exynos IP core.
109 this Freescale DSPI IP core. LS102xA and Colibri VF50/VF61 platforms
117 ICH IP core.
124 Marvell IP core.
189 this ST IP core.
196 IP core.
[all …]
/rk3399_rockchip-uboot/drivers/phy/
H A DKconfig67 Support for Rockchip USB 2.0 PHY with Innosilicon IP block.
81 Support for Rockchip USB 2.0 PHY with Naneng IP block.
88 Support for Rockchip USB 3.0 PHY with Innosilicon IP block.
95 Support for Rockchip eDP Transmitter PHY with Naneng IP block.
102 Support for Rockchip HDMI/DP Combo PHY with Samsung IP block.
109 Support for Rockchip PCIe3 PHY with Synopsys IP block.
117 combo PHY with Samsung IP block.
/rk3399_rockchip-uboot/drivers/bios_emulator/include/x86emu/
H A Dregs.h104 i386_general_register SP, BP, SI, DI, IP; member
151 #define R_IP spc.IP.I16_reg.x_reg
159 #define R_IP spc.IP.I16_reg.x_reg
167 #define R_EIP spc.IP.I32_reg.e_reg
/rk3399_rockchip-uboot/doc/device-tree-bindings/net/
H A Dsnps,dwc-qos-ethernet.txt1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
4 IP block. The IP supports multiple options for bus type, clocking and reset
12 Represents the IP core when integrated into the Axis ARTPEC-6 SoC.
14 Represents the IP core when integrated into the NVIDIA Tegra186 SoC.
22 - clock-names: May contain any/all of the following depending on the IP
56 Note: Support for additional IP configurations may require adding the
89 - reset-names: May contain any/all of the following depending on the IP
/rk3399_rockchip-uboot/drivers/usb/musb-new/
H A DKconfig27 silicon IP.
36 silicon IP.
/rk3399_rockchip-uboot/drivers/usb/dwc3/
H A DKconfig6 USB controller based on the DesignWare USB3 IP Core.
36 AM437x use this IP for USB2/3 functionality.
/rk3399_rockchip-uboot/drivers/video/drm/
H A DKconfig101 with Innosilicon IP block.
108 with Innosilicon IP block.
115 with Innosilicon IP block.
215 with SAMSUNG IP block.
223 IP block.
/rk3399_rockchip-uboot/doc/device-tree-bindings/clock/
H A Dst,stm32-rcc.txt4 The RCC IP is both a reset and a clock controller.
42 drivers of the RCC IP, macros are available to generate the index in
/rk3399_rockchip-uboot/board/birdland/bav335x/
H A DREADME30 the IP blocks, so both areas will need their choices updated to reflect
/rk3399_rockchip-uboot/doc/SPI/
H A DREADME.sh_qspi_test15 TFTP from server 192.168.169.1; our IP address is 192.168.169.79
/rk3399_rockchip-uboot/drivers/ata/
H A DKconfig47 This option enables Ceva Sata controller hard IP available on Xilinx
/rk3399_rockchip-uboot/doc/device-tree-bindings/video/
H A Dexynos-dp.txt7 reg: Base address of DP IP
/rk3399_rockchip-uboot/board/imgtec/xilfpga/
H A DREADME37 DDR initialization is already handled by a HW IP block.

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