Searched refs:GPIO3_IOC_BASE (Results 1 – 4 of 4) sorted by relevance
43 #define GPIO3_IOC_BASE GPIO2_IOC_BASE macro65 writel(0xffff1111, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_0); in board_set_iomux()66 writel(0x00ff0011, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_1); in board_set_iomux()68 writel(0x0ffc0554, GPIO3_IOC_BASE + GPIO3A_PULL); in board_set_iomux()89 writel(0xffff0000, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_0); in board_unset_iomux()90 writel(0x00ff0022, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_1); in board_unset_iomux()92 writel(0x0ffc0aa8, GPIO3_IOC_BASE + GPIO3A_PULL); in board_unset_iomux()
149 #define GPIO3_IOC_BASE 0xFF070000 macro203 #define UART2_RX_M1_ADDR (GPIO3_IOC_BASE + 0x40)207 #define UART2_TX_M1_ADDR (GPIO3_IOC_BASE + 0x40)222 #define UART3_RX_M1_ADDR (GPIO3_IOC_BASE + 0x50)226 #define UART3_TX_M1_ADDR (GPIO3_IOC_BASE + 0x4C)232 #define UART4_RX_M0_ADDR (GPIO3_IOC_BASE + 0x58)236 #define UART4_TX_M0_ADDR (GPIO3_IOC_BASE + 0x58)260 #define UART5_RX_M1_ADDR (GPIO3_IOC_BASE + 0x44)264 #define UART5_TX_M1_ADDR (GPIO3_IOC_BASE + 0x44)289 #define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x54)[all …]
79 #define GPIO3_IOC_BASE 0xFF560000 macro131 #define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x60)135 #define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x60)198 #define UART6_RX_M0_ADDR (GPIO3_IOC_BASE + 0x64)202 #define UART6_TX_M0_ADDR (GPIO3_IOC_BASE + 0x64)207 #define UART6_RX_M1_ADDR (GPIO3_IOC_BASE + 0x70)211 #define UART6_TX_M1_ADDR (GPIO3_IOC_BASE + 0x70)217 #define UART7_RX_M0_ADDR (GPIO3_IOC_BASE + 0x68)221 #define UART7_TX_M0_ADDR (GPIO3_IOC_BASE + 0x68)
124 #define GPIO3_IOC_BASE 0xFF558000 macro207 #define UART2_RX_M0_ADDR (GPIO3_IOC_BASE + 0x40)211 #define UART2_TX_M0_ADDR (GPIO3_IOC_BASE + 0x40)264 #define UART5_RX_M0_ADDR (GPIO3_IOC_BASE + 0x44)282 #define UART5_RX_M2_ADDR (GPIO3_IOC_BASE + 0x58)519 writel(0xfff01110, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_L); in arch_cpu_init()520 writel(0xffff1111, GPIO3_IOC_BASE + GPIO3A_IOMUX_SEL_H); in arch_cpu_init()