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/rk3399_rockchip-uboot/lib/
H A Dsha256.c88 uint32_t A, B, C, D, E, F, G, H; in sha256_process_one() local
137 G = ctx->state[6]; in sha256_process_one()
140 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process_one()
141 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process_one()
142 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process_one()
143 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process_one()
144 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process_one()
145 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process_one()
146 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process_one()
147 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process_one()
[all …]
H A Dsha512.c162 uint64_t A, B, C, D, E, F, G, H; in sha512_process() local
198 G = ctx->state[6]; in sha512_process()
203 P(A, B, C, D, E, F, G, H, W[i], K[i]); in sha512_process()
205 P(H, A, B, C, D, E, F, G, W[i], K[i]); in sha512_process()
207 P(G, H, A, B, C, D, E, F, W[i], K[i]); in sha512_process()
209 P(F, G, H, A, B, C, D, E, W[i], K[i]); in sha512_process()
211 P(E, F, G, H, A, B, C, D, W[i], K[i]); in sha512_process()
213 P(D, E, F, G, H, A, B, C, W[i], K[i]); in sha512_process()
215 P(C, D, E, F, G, H, A, B, W[i], K[i]); in sha512_process()
217 P(B, C, D, E, F, G, H, A, W[i], K[i]); in sha512_process()
[all …]
/rk3399_rockchip-uboot/arch/arm/dts/
H A Darmada-8040-mcbin.dts91 * [42,43] XSMI (controls two 10G phys)
94 * [49] 10G port 1 interrupt
95 * [50] 10G port 0 interrupt
96 * [51] 2.5G SFP TX fault
98 * [53] 2.5G SFP mode
99 * [54] 2.5G SFP LOS
166 * Lane 4: SFI (10G)
207 * [8] CP1 10G SFP LOS
208 * [9] CP1 10G PHY RESET
209 * [10] CP1 10G SFP TX Disable
[all …]
H A Dstm32mp157-pinctrl.dtsi169 pinmux = <STM32_PINMUX('G', 5, AF11)>, /* ETH_RGMII_CLK125 */
170 <STM32_PINMUX('G', 4, AF11)>, /* ETH_RGMII_GTX_CLK */
171 <STM32_PINMUX('G', 13, AF11)>, /* ETH_RGMII_TXD0 */
172 <STM32_PINMUX('G', 14, AF11)>, /* ETH_RGMII_TXD1 */
195 pinmux = <STM32_PINMUX('G', 5, ANALOG)>, /* ETH_RGMII_CLK125 */
196 <STM32_PINMUX('G', 4, ANALOG)>, /* ETH_RGMII_GTX_CLK */
197 <STM32_PINMUX('G', 13, ANALOG)>, /* ETH_RGMII_TXD0 */
198 <STM32_PINMUX('G', 14, ANALOG)>, /* ETH_RGMII_TXD1 */
314 <STM32_PINMUX('G', 10, AF11)>, /* QSPI_BK2_IO2 */
315 <STM32_PINMUX('G', 7, AF11)>; /* QSPI_BK2_IO3 */
[all …]
H A Dsun4i-a10-jesurun-q5.dts2 * Copyright 2015 Gábor Nyers
4 * Gábor Nyers <gabor.nyers@gmail.com>
/rk3399_rockchip-uboot/drivers/crypto/rockchip/
H A Dcrypto_ecc.c44 #define RK_LOAD_GROUP_A(G) do { \ argument
45 grp->curve_name = #G; \
46 grp->wide = G ## _wide;\
47 grp->p = G ## _p; \
48 grp->p_len = sizeof(G ## _p); \
49 grp->a = G ## _a; \
50 grp->a_len = sizeof(G ## _a); \
51 grp->n = G ## _n; \
52 grp->n_len = sizeof(G ## _n); \
53 grp->gx = G ## _gx; \
[all …]
/rk3399_rockchip-uboot/tools/rockchip/
H A Dresource_tool.c338 uint32_t A, B, C, D, E, F, G, H; in sha256_process() local
387 G = ctx->state[6]; in sha256_process()
390 P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98); in sha256_process()
391 P(H, A, B, C, D, E, F, G, W[1], 0x71374491); in sha256_process()
392 P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF); in sha256_process()
393 P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5); in sha256_process()
394 P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B); in sha256_process()
395 P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1); in sha256_process()
396 P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4); in sha256_process()
397 P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5); in sha256_process()
[all …]
/rk3399_rockchip-uboot/doc/
H A DREADME.mpc85xx57 Properties : 1M, AS1, I, G, IPROT
69 Properties : 1M, AS1, I, G
88 Properties : Board specific size, AS0, I, G, IPROT
98 Properties : 1M, AS1, I, G, IPROT
101 Properties : 4M, AS0, I, G, IPROT
109 Properties : 1M, AS1, I, G, IPROT
112 Properties : 4M, AS1, I, G, IPROT
125 Properties : 1M, AS1, I, G
137 Properties : 4M, AS1, I, G, IPROT
143 Properties : 4M, AS0, I, G, IPROT
[all …]
H A DREADME.sdp56 hid,uboot_header,1024,0x910000,0x10000000,1G,0x00900000,0x40000
72 hid,1024,0x10000000,1G,0x00907000,0x31000
88 hid,1024,0x910000,0x10000000,1G,0x00900000,0x40000
94 hid,uboot_header,1024,0x10000000,1G,0x00907000,0x31000
H A DREADME.zynq80 [1] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC702-G.htm
81 [2] http://www.xilinx.com/products/boards-and-kits/EK-Z7-ZC706-G.htm
/rk3399_rockchip-uboot/arch/x86/include/asm/arch-quark/acpi/
H A Dirqroute.h10 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_20, E, F, G, H), \
11 PCI_DEV_PIRQ_ROUTE(QUARK_DEV_21, E, F, G, H), \
/rk3399_rockchip-uboot/arch/x86/include/asm/fsp/
H A Dfsp_types.h68 #define SIGNATURE_64(A, B, C, D, E, F, G, H) \ argument
69 (SIGNATURE_32(A, B, C, D) | ((u64)(SIGNATURE_32(E, F, G, H)) << 32))
/rk3399_rockchip-uboot/board/freescale/t208xrdb/
H A DREADME40 1G Ethernet numbers: 8 6
41 10G Ethernet numbers: 4 2
52 - SerDes-1 Lane A-B: to two 10G XFI fiber (MAC9 & MAC10)
53 - SerDes-1 Lane C-D: to two 10G Base-T (MAC1 & MAC2)
57 - SerDes-2 Lane G-H: to SATA1 & SATA2
59 - Two on-board 10M/100M/1G RGMII ethernet ports
131 ETH0 FM1@GTEC1 fm1-mac9 0xfe4f0000 10G SFP+ (CS4315)
132 ETH1 FM1@GTEC2 fm1-mac10 0xfe4f2000 10G SFP+ (CS4315)
133 ETH2 FM1@GTEC3 fm1-mac1 0xfe4e0000 10G Base-T (AQ1202)
134 ETH3 FM1@GTEC4 fm1-mac2 0xfe4e2000 10G Base-T (AQ1202)
[all …]
/rk3399_rockchip-uboot/board/freescale/t208xqds/
H A DREADME40 1G Ethernet numbers: 8 6
41 10G Ethernet numbers: 4 2
107 1000BASE-KX(1G-KX):
108 - T2080QDS can support 1G-KX by using SGMII protocol, but serdes lane
109 runs in 1G-KX mode. By default, the lane runs in SGMII mode, to set a lane
110 in 1G-KX mode, need to set corresponding bit in SerDes Protocol Configuration
113 Hwconfig "fsl_1gkx" is used to indicate a lane runs in 1G-KX mode, MAC
114 1/2/5/6/9/10 are available for 1G-KX, MAC 3/4 run in RGMII mode. To set a
115 MAC to use 1G-KX mode, set its' corresponding env in "fsl_1gkx", 'fm1_1g1'
118 hwconfig, MAC 1/2/5/6/9/10 will use 1G-KX mode.
/rk3399_rockchip-uboot/board/freescale/ls1046ardb/
H A DREADME55 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
56 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
57 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
/rk3399_rockchip-uboot/board/freescale/ls1046aqds/
H A DREADME60 0x40_0000_0000 - 0x47_FFFF_FFFF PCI Express1 32G
61 0x48_0000_0000 - 0x4F_FFFF_FFFF PCI Express2 32G
62 0x50_0000_0000 - 0x57_FFFF_FFFF PCI Express3 32G
/rk3399_rockchip-uboot/board/congatec/
H A DKconfig19 (conga-QEVAL) equipped with the conga-QA3/E3845-4G SoM.
31 conga-QA3/E3845-4G SoM. It contains an Atom E3845 with Ethernet,
/rk3399_rockchip-uboot/board/freescale/mpc837xerdb/
H A DREADME17 G) 1 32-bit, 3.3 V, PCI slot
40 0x1000_0000 0x7fff_ffff Empty 1.75G -
/rk3399_rockchip-uboot/drivers/net/phy/
H A Dteranetics.c14 #error The Teranetics PHY needs 10G support
/rk3399_rockchip-uboot/configs/
H A Dvinco_defconfig34 CONFIG_USB_GADGET_MANUFACTURER="L+G VInCo"
/rk3399_rockchip-uboot/board/freescale/p1010rdb/
H A DREADME.P1010RDB-PB15 - 1G bytes unbuffered DDR3 SDRAM discrete devices (32-bit bus)
17 - 2G bytes NAND flash memory
42 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
43 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
H A DREADME.P1010RDB-PA26 - 1 internal SATA connector to 2.5” 160G SATA2 HDD
60 0x0000_0000 0x3fff_ffff DDR 1G Cacheable
61 0xa000_0000 0xdfff_ffff PCI Express Mem 1G non-cacheable
/rk3399_rockchip-uboot/arch/arm/cpu/armv8/fsl-layerscape/doc/
H A DREADME.soc30 - Up to 1 x XFI supporting 10G interface
155 - Support for 10G operation
157 - Up to 2 x XFI supporting 10G interface (MAC 9, 10)
226 c) 5 * 1/10G + 5 *1G WRIOP
/rk3399_rockchip-uboot/board/freescale/t102xrdb/
H A DREADME79 - Two on-board 10M/100M/1G bps RGMII ethernet ports
80 - One on-board 10G bps Base-T port.
110 - one 1G RGMII port on-board(RTL8211FS PHY)
111 - one 1G SGMII port on-board(RTL8211FS PHY)
112 - one 2.5G SGMII port on-board(AQR105 PHY)
/rk3399_rockchip-uboot/board/freescale/ls1021aiot/
H A DREADME16 - Two on-board SGMII 10/100/1G ethernet ports

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