Searched refs:FSEL (Results 1 – 2 of 2) sorted by relevance
120 clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); in board_clock_init()121 set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); in board_clock_init()204 set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); in board_clock_init()
15 #define FSEL(x) (((x) & 0x1) << 27) macro