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Searched refs:FIREWALL_DDR_BASE (Results 1 – 4 of 4) sorted by relevance

/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3528/
H A Drk3528.c17 #define FIREWALL_DDR_BASE 0xff2e0000 macro
400 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG); in arch_cpu_init()
401 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG); in arch_cpu_init()
404 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST14_REG); in arch_cpu_init()
405 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST14_REG); in arch_cpu_init()
408 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
409 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
413 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST7_REG); in arch_cpu_init()
414 writel(val & 0xffff0000, FIREWALL_DDR_BASE + FW_DDR_MST7_REG); in arch_cpu_init()
441 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST16_REG); in arch_cpu_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3506/
H A Drk3506.c26 #define FIREWALL_DDR_BASE 0xff5f0000 macro
141 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
142 writel(val & 0xffff00ff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
149 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
150 writel(val & 0xff00ffff, FIREWALL_DDR_BASE + FW_DDR_MST1_REG); in arch_cpu_init()
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3588/
H A Drk3588.c21 #define FIREWALL_DDR_BASE 0xfe030000 macro
927 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG); in arch_cpu_init()
929 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST5_REG); in arch_cpu_init()
930 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST13_REG); in arch_cpu_init()
932 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST13_REG); in arch_cpu_init()
933 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST21_REG); in arch_cpu_init()
935 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST21_REG); in arch_cpu_init()
936 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST26_REG); in arch_cpu_init()
938 writel(secure_reg, FIREWALL_DDR_BASE + FW_DDR_MST26_REG); in arch_cpu_init()
939 secure_reg = readl(FIREWALL_DDR_BASE + FW_DDR_MST27_REG); in arch_cpu_init()
[all …]
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3562/
H A Drk3562.c23 #define FIREWALL_DDR_BASE 0xfef00000 macro
641 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST4_REG); in arch_cpu_init()
642 writel(val & 0x0000ffff, FIREWALL_DDR_BASE + FW_DDR_MST4_REG); in arch_cpu_init()
645 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST6_REG); in arch_cpu_init()
646 writel(val & 0xff0000ff, FIREWALL_DDR_BASE + FW_DDR_MST6_REG); in arch_cpu_init()
669 val = readl(FIREWALL_DDR_BASE + FW_DDR_MST5_REG); in arch_cpu_init()
670 writel(val & 0x00ffffff, FIREWALL_DDR_BASE + FW_DDR_MST5_REG); in arch_cpu_init()