Searched refs:EPLL (Results 1 – 5 of 5) sorted by relevance
141 if (pllreg == EPLL || pllreg == RPLL) { in exynos_get_pll_clk()199 case EPLL: in exynos4_get_pll_clk()229 case EPLL: in exynos4x12_get_pll_clk()260 case EPLL: in exynos5_get_pll_clk()318 case EPLL: in exynos542x_get_pll_clk()441 sclk = exynos5_get_pll_clk(EPLL); in exynos5_get_periph_rate()535 sclk = exynos542x_get_pll_clk(EPLL); in exynos542x_get_periph_rate()655 sclk = get_pll_clk(EPLL); in exynos4_get_pwm_clk()716 sclk = get_pll_clk(EPLL); in exynos4_get_uart_clk()762 sclk = get_pll_clk(EPLL); in exynos4x12_get_uart_clk()[all …]
14 #define EPLL 2 macro
13 #define EPLL 2 macro
40 case EPLL: in s5pc100_get_pll_clk()91 case EPLL: in s5pc110_get_pll_clk()
55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)