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Searched refs:DSP (Results 1 – 12 of 12) sorted by relevance

/rk3399_rockchip-uboot/doc/
H A DREADME.Heterogeneous-SoCs1 DSP side awareness for Freescale heterogeneous multicore chips based on
7 SC3900/DSP cores and such devices like CPRI, MAPLE, MAPLE-ULB etc.
9 Code for DSP side awareness provides such functionality for Freescale
19 Code added in this file to print the DSP cores and other device's(CPRI,
35 in the system and CONFIGS for SC3900/DSP components
50 DSP/SC3900 core clusters
73 DSP cores and other device's components have been added in this structure.
75 freq_processor_dsp[CONFIG_MAX_DSP_CPUS] - Array to contain the DSP core's frequencies
91 DSP CPU0:1200 MHz, DSP CPU1:1200 MHz, DSP CPU2:1200 MHz, DSP CPU3:1200 MHz,
92 DSP CPU4:1200 MHz, DSP CPU5:1200 MHz,
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H A DREADME.davinci9 Additionally, some family members contain a TI DSP and/or graphics
H A DREADME.omap37 some family members contain a TMS320C64x+ DSP and/or an Imagination SGX 2D/3D
/rk3399_rockchip-uboot/board/freescale/bsc9131rdb/
H A DREADME4 It combines Power Architecture e500v2 and DSP StarCore SC3850 core
11 . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
104 0xA0000000 0xBFFFFFFF Shared DSP core L2/M2 space 512M
109 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
110 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
117 0x3700_0000 0x37FF_FFFF PowerPC-DSP shared control area
118 0x3800_0000 0x4FFF_FFFF DSP Private area
121 data communcation between PowerPC and DSP core.
/rk3399_rockchip-uboot/board/freescale/bsc9132qds/
H A DREADME6 The BSC9132 device combines Power Architecture e500 and DSP StarCore SC3850
17 - Two StarCore SC3850 DSP subsystems, each with a 512-Kbyte private L2
109 0xA000_0000 0xA7FF_FFFF DSP core1 L2 space 128M
110 0xB000_0000 0xB0FF_FFFF DSP core0 M2 space 16M
111 0xB100_0000 0xB1FF_FFFF DSP core1 M2 space 16M
118 0xFEE0_0000 0xFEE0_0FFF DSP Boot ROM 4K
119 0xFF60_0000 0xFF6F_FFFF DSP CCSR 1M
/rk3399_rockchip-uboot/include/
H A Dsym53c8xx.h130 #define DSP 0x2c /* --> Script Pointer */ macro
/rk3399_rockchip-uboot/arch/arm/dts/
H A Ddra71-evm.dts66 /* FB_B1 -> LP8733-BUCK2 - VPO_S2_AVS - VDD_DSP_AVS (DSP/eve/iva) */
/rk3399_rockchip-uboot/board/Barix/ipam390/
H A Dipam390-ais-uart.cfg183 ; for starting the DDR2 interface on DSP-boot D800K002 devices.
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/rk3288/
H A DKconfig46 The EVB-RK3288-RK1608 includes a Host AP RK3288 and a DSP coprocessor
/rk3399_rockchip-uboot/board/ti/ks2_evm/
H A DREADME97 to configure SW1 dip switch to use "No Boot/JTAG DSP Little Endian Boot Mode"
/rk3399_rockchip-uboot/arch/arm/mach-rockchip/
H A DKconfig670 and a DSP.
/rk3399_rockchip-uboot/
H A DREADME380 connected exclusively to the DSP cores.
384 which is directly connected to the DSP core.
388 connected to the DSP core.
391 This value denotes start offset of DSP CCSR space.