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Searched refs:DP_LANE0_1_STATUS (Results 1 – 6 of 6) sorted by relevance

/rk3399_rockchip-uboot/drivers/video/drm/
H A Ddrm_dp_helper.c39 return link_status[r - DP_LANE0_1_STATUS]; in dp_link_status()
45 int i = DP_LANE0_1_STATUS + (lane >> 1); in dp_get_lane_status()
235 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, in drm_dp_dpcd_read_link_status()
H A Danalogix_dp.c383 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); in analogix_dp_process_clock_recovery()
464 retval = drm_dp_dpcd_read(&dp->aux, DP_LANE0_1_STATUS, link_status, 2); in analogix_dp_process_equalizer_training()
/rk3399_rockchip-uboot/include/linux/
H A Ddrm_dp_helper.h250 #define DP_LANE0_1_STATUS 0x202 macro
/rk3399_rockchip-uboot/drivers/video/tegra124/
H A Ddp.c779 DP_LANE2_3_STATUS : DP_LANE0_1_STATUS, in tegra_dc_dp_link_trained()
806 ret = tegra_dc_dp_dpcd_read(dp, DP_LANE0_1_STATUS + cnt, &data); in tegra_dp_channel_eq_status()
849 ret = tegra_dc_dp_dpcd_read(dp, (DP_LANE0_1_STATUS + cnt), in tegra_dp_clock_recovery_status()
1264 DP_LANE0_1_STATUS, (u8 *)&data16, &size, &status); in tegra_dc_dp_fast_link_training()
1283 tegra_dc_dpaux_read(dp, DPAUX_DP_AUXCTL_CMD_AUXRD, DP_LANE0_1_STATUS, in tegra_dc_dp_fast_link_training()
/rk3399_rockchip-uboot/drivers/video/drm/display-serdes/maxim/
H A Dmaxim-max96772.c430 ret = max96772_aux_dpcd_read(serdes, DP_LANE0_1_STATUS, &status[0]); in max96772_panel_enable()
/rk3399_rockchip-uboot/include/drm/
H A Ddrm_dp_helper.h556 #define DP_LANE0_1_STATUS 0x202 macro