Searched refs:CLK_PMU1_PWM0_DIV_SHIFT (Results 1 – 2 of 2) sorted by relevance
286 CLK_PMU1_PWM0_DIV_SHIFT = 8, enumerator287 CLK_PMU1_PWM0_DIV_MASK = 0x3 << CLK_PMU1_PWM0_DIV_SHIFT,
639 div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT; in rk3562_pwm_get_rate()693 (div - 1) << CLK_PMU1_PWM0_DIV_SHIFT); in rk3562_pwm_set_rate()