Searched refs:CLK_PMU1_PWM0_DIV_MASK (Results 1 – 2 of 2) sorted by relevance
287 CLK_PMU1_PWM0_DIV_MASK = 0x3 << CLK_PMU1_PWM0_DIV_SHIFT, enumerator
639 div = (con & CLK_PMU1_PWM0_DIV_MASK) >> CLK_PMU1_PWM0_DIV_SHIFT; in rk3562_pwm_get_rate()692 rk_clrsetreg(&cru->pmu1clksel_con[4], CLK_PMU1_PWM0_DIV_MASK, in rk3562_pwm_set_rate()