Searched refs:CLK_PLL1_DIV2 (Results 1 – 2 of 2) sorted by relevance
| /rk3399_rockchip-uboot/drivers/clk/renesas/ |
| H A D | clk-rcar-gen3.c | 172 CLK_PLL1_DIV2, enumerator
199 DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
200 DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
201 DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
202 DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
203 DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
204 DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
205 DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
208 DEF_FIXED("ztr", R8A7795_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
209 DEF_FIXED("ztrd2", R8A7795_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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| /rk3399_rockchip-uboot/drivers/phy/ |
| H A D | phy-rockchip-typec.c | 85 #define CLK_PLL1_DIV2 0x30 macro
138 rdata |= CLK_PLL1_DIV2; in tcphy_cfg_24m()
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