Home
last modified time | relevance | path

Searched refs:so (Results 1 – 25 of 77) sorted by relevance

1234

/rk3399_ARM-atf/plat/nvidia/tegra/scat/
H A Dbl31.scat63 * Ensure 8-byte alignment for cpu_ops so that its fields are also
74 * security. GOT is a table of addresses so ensure 8-byte alignment.
103 * address, but we need to place them in a separate page so that we can set
104 * individual permissions to them, so the actual alignment needed is 4K.
135 * this section correctly. Ensure 8-byte alignment so that the fields of
/rk3399_ARM-atf/docs/plat/
H A Drpi4.rst14 not seem to feature a secure memory controller of any kind, so portions of
20 There are no real configuration options at this point, so there is only
56 There is not so much difference between the two models, so eventually those
63 filesystem, so it will load further components and configuration files
H A Dmeson-axg.rst12 can't be turned off, so there is a workaround to hide this from the caller.
H A Dmeson-gxbb.rst12 can't be turned off, so there is a workaround to hide this from the caller.
H A Dmeson-g12a.rst12 can't be turned off, so there is a workaround to hide this from the caller.
H A Drpi3.rst62 between them so that the addresses they are loaded to match the ones specified
131 so that the kernel doesn't use it. The current port tries to modify the live DTB
141 the end of the DRAM, so this space isn't wasted.
150 kernel. In that case, BL33 is booted in AArch32 Hypervisor mode so that it
170 The kernel used by `Raspbian`_ doesn't have support for PSCI, so it is needed to
185 address to the mailbox so that the secondary CPUs jump to it and are recognised
197 The build system concatenates BL1 and the FIP so that the addresses match the
275 Linux command line so that the USB driver doesn't use FIQs:
296 address by changing the file ``armstub8.bin``, so there's no point in using
372 2. Configure and compile the kernel. Adapt the number after ``-j`` so that it is
H A Dmeson-gxl.rst12 can't be turned off, so there is a workaround to hide this from the caller.
H A Drockchip.rst36 integrated with other boot software like U-Boot or Coreboot, so only
H A Drpi5.rst12 not seem to feature a secure memory controller of any kind, so portions of
/rk3399_ARM-atf/docs/plat/arm/arm_fpga/
H A Dindex.rst8 Some interconnect setup is done internally by the platform, so the TF-A code
12 (mostly Linux), so we let TF-A use information from the DTB for dynamic
45 so it must describe at least the UART and a GICv3 interrupt controller.
54 a command line can be put somewhere into memory, so that BL31 will
/rk3399_ARM-atf/licenses/
H A DLICENSE.MIT10 furnished to do so, subject to the following conditions:
/rk3399_ARM-atf/tools/cot_dt2c/
H A D.gitignore11 *.so
35 # before PyInstaller builds the exe, so as to inject date/other infos into it.
/rk3399_ARM-atf/lib/compiler-rt/
H A DLICENSE.TXT34 so, subject to the following conditions:
65 furnished to do so, subject to the following conditions:
/rk3399_ARM-atf/docs/plat/qti/
H A Dchrome.rst27 Coreboot, so only bl31.elf need to get build from the TF-A repository.
/rk3399_ARM-atf/docs/components/
H A Dnuma-per-cpu.rst79 bounds and per-object stride via internal symbols so that they can be replicated
120 Declares an external per-CPU object so that other translation units can refer
125 Defines a per-CPU object and assigns it to ``PER_CPU_SECTION_NAME`` so the
187 The platform is free to maintain this mapping however it prefers, and may do so
H A Dexception-handling.rst159 set to ``1`` so that *Group 0* interrupts target EL3.
333 /* Dispatcher 1 owns interrupts d1_0 and d1_1, so assigns priority DISP1_PRIO */
337 /* Dispatcher 2 owns interrupts d2_0 and d2_1, so assigns priority DISP2_PRIO */
341 /* Dispatcher 3 owns interrupts d3_0 and d3_1, so assigns priority DISP3_PRIO */
486 example), so will vary across dispatchers that handle the request.
489 to be taken to S-EL1 [#irq]_, so would get a chance to populate the designated
609 demand so.
/rk3399_ARM-atf/fdts/
H A Darm_fpga.dts6 * Number and kind of CPU cores differs from image to image, so the
H A Dstm32mp151a-prtt1a.dts214 * reason, so it should do no harm. All inputs configured with
/rk3399_ARM-atf/docs/
H A Darchitecture_features.rst473 If it is defined to 1, the code will use the feature unconditionally, so the CPU
478 but its existence will be checked at runtime, so it works on CPUs with or
496 do this, so please consult with previous such patches and/or maintainers. Please
/rk3399_ARM-atf/plat/arm/board/fvp/fdts/
H A Dfvp_tb_fw_config.dts119 /* FVP does not support the CCA NV Counter so use the Trusted one. */
/rk3399_ARM-atf/docs/components/spd/
H A Dtlk-dispatcher.rst7 so while TF-A only supports TLK on Tegra, the dispatcher code can only be
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-13.rst76 Arm has updated the SMC Calling Convention spec so that privileged normal world
H A Dsecurity-advisory-tfv-10.rst94 ``get_ext()``, which means that the second bug is exploitable, so is the first.
122 so no memory corruption is possible.
/rk3399_ARM-atf/docs/design/
H A Dtrusted-board-boot-build.rst39 accordingly so it points at the OpenSSL installation path, as explained in
41 when running to point at the custom OpenSSL path, so the OpenSSL libraries
/rk3399_ARM-atf/plat/allwinner/common/
H A Darisc_off.S20 # r3, so to be patched in the lower 16 bits of the first instruction,

1234