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Searched refs:per_cpu (Results 1 – 13 of 13) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc.c42 uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); in spm_enable_cpu_auto_off()
50 uintptr_t reg = per_cpu(cluster, cpu, MCUCFG_SPARK); in spm_disable_cpu_auto_off()
58 mmio_clrbits_32(per_cpu(cluster, cpu, SPM_CPU_PWR), PWRCTRL_PWR_ON); in spm_set_cpu_power_off()
84 reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); in mcucfg_set_bootaddr()
101 reg = per_cpu(cluster, cpu, MCUCFG_BOOTADDR); in mcucfg_get_bootaddr()
170 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
171 mmio_clrbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
172 mmio_clrbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
173 mmio_clrbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWRCTRL_PWR_ON_2ND); in spmc_init()
175 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWRCTRL_PWR_RST_B); in spmc_init()
[all …]
H A Dmtspmc_private.h18 #define per_cpu(cluster, cpu, reg) (reg[cluster].cluster_addr + \ macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/
H A Dmtspmc.c32 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
39 return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); in mcucfg_get_bootaddr()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
[all …]
H A Dmtspmc_private.h27 #define per_cpu(cluster, cpu, reg) \ macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc.c34 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
41 return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); in mcucfg_get_bootaddr()
98 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
100 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
101 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
102 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
103 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
104 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
108 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
[all …]
H A Dmtspmc_private.h25 #define per_cpu(cluster, cpu, reg) \ macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/
H A Dmtspmc.c32 mmio_write_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR), bootaddr); in mcucfg_set_bootaddr()
39 return (uintptr_t)mmio_read_32(per_cpu(cluster, cpu, MCUCFG_BOOTADDR)); in mcucfg_get_bootaddr()
93 mmio_setbits_32(per_cpu(0, 1, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
94 mmio_setbits_32(per_cpu(0, 2, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
95 mmio_setbits_32(per_cpu(0, 3, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
96 mmio_setbits_32(per_cpu(0, 4, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
97 mmio_setbits_32(per_cpu(0, 5, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
98 mmio_setbits_32(per_cpu(0, 6, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
99 mmio_setbits_32(per_cpu(0, 7, SPM_CPU_PWR), PWR_RST_B); in spmc_init()
111 mmio_clrbits_32(per_cpu(0, 0, SPM_CPU_PWR), RESETPWRON_CONFIG); in spmc_init()
[all …]
H A Dmtspmc_private.h27 #define per_cpu(cluster, cpu, reg) \ macro
/rk3399_ARM-atf/bl32/sp_min/
H A Dsp_min.mk20 lib/per_cpu/per_cpu.c \
/rk3399_ARM-atf/docs/components/
H A Dnuma-per-cpu.rst56 ``.per_cpu`` Section
59 The framework dedicates a zero-initialized, cache-aligned ``.per_cpu`` section
70 enabled, Node 0 includes an additional \`.per_cpu\` section between
108 (``.per_cpu``).
126 linker emits it into the ``.per_cpu`` section that the framework manages.
137 combining the per-node base with the object's offset within ``.per_cpu``.
174 Ensure that the platform can supply the base address of the ``.per_cpu`` section
191 corresponding ``.per_cpu`` section.
205 Returns the base address of the ``.per_cpu`` section for the specified CPU.
209 Returns the base address of the ``.per_cpu`` section for the specified node.
/rk3399_ARM-atf/include/common/
H A Dbl_common.ld.h230 .per_cpu (NOLOAD) : ALIGN(CACHE_WRITEBACK_GRANULE) { \
233 *(SORT_BY_ALIGNMENT(.per_cpu*)) \
/rk3399_ARM-atf/bl31/
H A Dbl31.mk45 lib/per_cpu/aarch64/per_cpu_asm.S \
46 lib/per_cpu/per_cpu.c \
/rk3399_ARM-atf/docs/about/
H A Dmaintainers.rst536 :|F|: include/lib/per_cpu
537 :|F|: lib/per_cpu