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Searched refs:pd (Results 1 – 21 of 21) sorted by relevance

/rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/
H A Dlpddr4.c19 static uint32_t lpddr4_pollctlirq(const ti_lpddr4_privatedata *pd, in lpddr4_pollctlirq() argument
32 result = ti_lpddr4_checkctlinterrupt(pd, irqbit, &irqstatus); in lpddr4_pollctlirq()
38 static uint32_t lpddr4_pollphyindepirq(const ti_lpddr4_privatedata *pd, in lpddr4_pollphyindepirq() argument
51 result = ti_lpddr4_checkphyindepinterrupt(pd, irqbit, &irqstatus); in lpddr4_pollphyindepirq()
57 static uint32_t lpddr4_pollandackirq(const ti_lpddr4_privatedata *pd) in lpddr4_pollandackirq() argument
60 lpddr4_ctlregs *ctlregbase = pd->ctlbase; in lpddr4_pollandackirq()
62 result = lpddr4_pollphyindepirq(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT, in lpddr4_pollandackirq()
71 result = ti_lpddr4_ackphyindepinterrupt(pd, LPDDR4_INTR_PHY_INDEP_INIT_DONE_BIT); in lpddr4_pollandackirq()
76 result = lpddr4_pollctlirq(pd, LPDDR4_INTR_MC_INIT_DONE, TI_LPDDR4_CUSTOM_TIMEOUT_DELAY); in lpddr4_pollandackirq()
84 result = ti_lpddr4_ackctlinterrupt(pd, LPDDR4_INTR_MC_INIT_DONE); in lpddr4_pollandackirq()
[all …]
H A Dlpddr4_16bit_sanity.h16 static inline uint32_t ti_lpddr4_intr_ctlint_sf(const ti_lpddr4_privatedata *pd, in ti_lpddr4_intr_ctlint_sf() argument
22 if (pd == NULL) { in ti_lpddr4_intr_ctlint_sf()
33 static inline uint32_t ti_lpddr4_intr_ack_ctlint_sf(const ti_lpddr4_privatedata *pd, in ti_lpddr4_intr_ack_ctlint_sf() argument
38 if (pd == NULL) { in ti_lpddr4_intr_ack_ctlint_sf()
47 static inline uint32_t ti_lpddr4_intr_phyint_sf(const ti_lpddr4_privatedata *pd, in ti_lpddr4_intr_phyint_sf() argument
53 if (pd == NULL) { in ti_lpddr4_intr_phyint_sf()
64 static inline uint32_t ti_lpddr4_intr_ack_phyint_sf(const ti_lpddr4_privatedata *pd, in ti_lpddr4_intr_ack_phyint_sf() argument
69 if (pd == NULL) { in ti_lpddr4_intr_ack_phyint_sf()
H A Dam62l_ddrss.c92 ti_lpddr4_privatedata pd; member
209 static void k3_lpddr4_ack_freq_upd_req(const ti_lpddr4_privatedata *pd) in k3_lpddr4_ack_freq_upd_req() argument
215 static void k3_lpddr4_info_handler(const ti_lpddr4_privatedata *pd, in k3_lpddr4_info_handler() argument
219 k3_lpddr4_ack_freq_upd_req(pd); in k3_lpddr4_info_handler()
231 ti_lpddr4_privatedata *pd = &ddrss.pd; in am62l_lpddr4_init() local
310 status = driverdt->init(pd, config); in am62l_lpddr4_init()
318 driverdt->writectlconfigex(pd, am62lx_ddr_cfg.ctl_data, in am62l_lpddr4_init()
320 driverdt->writephyindepconfigex(pd, am62lx_ddr_cfg.pi_data, in am62l_lpddr4_init()
322 driverdt->writephyconfigex(pd, am62lx_ddr_cfg.phy_data, in am62l_lpddr4_init()
326 driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, &regval); in am62l_lpddr4_init()
[all …]
H A Dlpddr4_16bit.c80 void ti_lpddr4_enable_pi_initiator(const ti_lpddr4_privatedata *pd) in ti_lpddr4_enable_pi_initiator() argument
84 lpddr4_ctlregs *ctlregbase = pd->ctlbase; in ti_lpddr4_enable_pi_initiator()
94 uint32_t ti_lpddr4_checkctlinterrupt(const ti_lpddr4_privatedata *pd, in ti_lpddr4_checkctlinterrupt() argument
103 result = ti_lpddr4_intr_ctlint_sf(pd, intr, irqstatus); in ti_lpddr4_checkctlinterrupt()
108 lpddr4_ctlregs *ctlregbase = pd->ctlbase; in ti_lpddr4_checkctlinterrupt()
213 uint32_t ti_lpddr4_ackctlinterrupt(const ti_lpddr4_privatedata *pd, in ti_lpddr4_ackctlinterrupt() argument
220 result = ti_lpddr4_intr_ack_ctlint_sf(pd, intr); in ti_lpddr4_ackctlinterrupt()
228 ctlregbase = pd->ctlbase; in ti_lpddr4_ackctlinterrupt()
H A Dlpddr4.h25 void ti_lpddr4_enable_pi_initiator(const ti_lpddr4_privatedata *pd);
/rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/common/
H A Dlpddr4_if.h34 typedef void (*lpddr4_infocallback)(const ti_lpddr4_privatedata *pd, ti_lpddr4_infotype infotype);
36 typedef void (*lpddr4_ctlcallback)(const ti_lpddr4_privatedata *pd,
40 typedef void (*lpddr4_phyindepcallback)(const ti_lpddr4_privatedata *pd,
46 uint32_t ti_lpddr4_init(ti_lpddr4_privatedata *pd, const ti_lpddr4_config *cfg);
48 uint32_t ti_lpddr4_start(const ti_lpddr4_privatedata *pd);
50 uint32_t ti_lpddr4_readreg(const ti_lpddr4_privatedata *pd, ti_lpddr4_regblock cpp,
53 uint32_t ti_lpddr4_writereg(const ti_lpddr4_privatedata *pd, ti_lpddr4_regblock cpp,
56 uint32_t ti_lpddr4_writectlconfigex(const ti_lpddr4_privatedata *pd,
59 uint32_t ti_lpddr4_writephyconfigex(const ti_lpddr4_privatedata *pd,
62 uint32_t ti_lpddr4_writephyindepconfigex(const ti_lpddr4_privatedata *pd,
[all …]
H A Dlpddr4_obj_if.h16 uint32_t (*init)(ti_lpddr4_privatedata *pd, const ti_lpddr4_config *cfg);
17 uint32_t (*start)(const ti_lpddr4_privatedata *pd);
18 uint32_t (*readreg)(const ti_lpddr4_privatedata *pd, ti_lpddr4_regblock cpp,
20 uint32_t (*writereg)(const ti_lpddr4_privatedata *pd, ti_lpddr4_regblock cpp,
22 uint32_t (*writectlconfigex)(const ti_lpddr4_privatedata *pd,
24 uint32_t (*writephyconfigex)(const ti_lpddr4_privatedata *pd,
26 uint32_t (*writephyindepconfigex)(const ti_lpddr4_privatedata *pd,
28 uint32_t (*checkctlinterrupt)(const ti_lpddr4_privatedata *pd,
30 uint32_t (*ackctlinterrupt)(const ti_lpddr4_privatedata *pd,
32 uint32_t (*checkphyindepinterrupt)(const ti_lpddr4_privatedata *pd,
[all …]
/rk3399_ARM-atf/plat/rockchip/common/drivers/pmu/
H A Dpmu_com.h36 static inline uint32_t pmu_power_domain_st(uint32_t pd) in pmu_power_domain_st() argument
38 uint32_t pwrdn_st = mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd); in pmu_power_domain_st()
46 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) in pmu_power_domain_ctr() argument
56 val |= BIT(pd); in pmu_power_domain_ctr()
58 val &= ~BIT(pd); in pmu_power_domain_ctr()
63 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { in pmu_power_domain_ctr()
68 if (pmu_power_domain_st(pd) != pd_state) { in pmu_power_domain_ctr()
69 WARN("%s: %d, %d, error!\n", __func__, pd, pd_state); in pmu_power_domain_ctr()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/apusys/
H A Dapupll.c238 static int32_t _cal_pll_data(uint32_t *pd, uint32_t *dds, uint32_t freq) in _cal_pll_data() argument
260 *pd = postdiv_reg; in _cal_pll_data()
510 uint32_t pd, old_pd, dds; in anpu_pll_set_rate() local
519 _cal_pll_data(&pd, &dds, freq / 1000); in anpu_pll_set_rate()
522 __func__, pllidx2name(pll_idx), pd, dds, freq / 1000, mode); in anpu_pll_set_rate()
536 pd = RG_PLL_SDM_PCW_CHG | in anpu_pll_set_rate()
537 (pd & POSDIV_MASK) << POSDIV_SHIFT | dds; in anpu_pll_set_rate()
538 apupwr_writel(pd, mixed_con1_addr[pll_idx]); in anpu_pll_set_rate()
545 _set_postdiv_reg(pll_idx, pd); in anpu_pll_set_rate()
554 if (pd > old_pd) { in anpu_pll_set_rate()
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/rk3399_ARM-atf/lib/libc/
H A Dqsort.c106 char *pa, *pb, *pc, *pd, *pl, *pm, *pn; in local_qsort() local
140 pc = pd = (char *)a + (n - 1) * es; in local_qsort()
153 swapfunc(pc, pd, es); in local_qsort()
154 pd -= es; in local_qsort()
182 d1 = MIN(pd - pc, pn - pd - (ssize_t)es); in local_qsort()
186 d2 = pd - pc; in local_qsort()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c291 static inline uint32_t pmu_power_domain_chain_st(uint32_t pd) in pmu_power_domain_chain_st() argument
293 return mmio_read_32(PMU_BASE + PMU2_PWR_CHAIN1_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_chain_st()
298 static inline uint32_t pmu_power_domain_mem_st(uint32_t pd) in pmu_power_domain_mem_st() argument
300 return mmio_read_32(PMU_BASE + PMU2_PWR_MEM_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_mem_st()
305 static inline uint32_t pmu_power_domain_st(uint32_t pd) in pmu_power_domain_st() argument
307 int8_t pd_repair = pd_repair_map[pd]; in pmu_power_domain_st()
314 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST(pd / 32)) & BIT(pd % 32) ? in pmu_power_domain_st()
319 static int pmu_power_domain_pd_to_mem_st(uint32_t pd, uint32_t *pd_mem_st) in pmu_power_domain_pd_to_mem_st() argument
323 switch (pd) { in pmu_power_domain_pd_to_mem_st()
405 static int pmu_power_domain_reset_mem(uint32_t pd, uint32_t pd_mem_st) in pmu_power_domain_reset_mem() argument
[all …]
/rk3399_ARM-atf/plat/rockchip/rk3368/drivers/pmu/
H A Dpmu.c245 uint32_t pd; in cpus_id_power_domain() local
249 pd = PD_CPUB0 + cpu; in cpus_id_power_domain()
251 pd = PD_CPUL0 + cpu; in cpus_id_power_domain()
253 if (pmu_power_domain_st(pd) == pd_state) in cpus_id_power_domain()
262 return pmu_power_domain_ctr(pd, pd_state); in cpus_id_power_domain()
/rk3399_ARM-atf/docs/design/
H A Dindex.rst13 psci-pd-tree
/rk3399_ARM-atf/plat/mediatek/drivers/gpio/
H A Dmtgpio_common.c189 uint32_t pd; in mt_gpio_get_pull_pu_pd() local
199 pd = (mmio_read_32(reg2) >> bit) & 1U; in mt_gpio_get_pull_pu_pd()
202 } else if (pd == 1U) { in mt_gpio_get_pull_pu_pd()
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c422 static inline uint32_t pmu_power_domain_st(uint32_t pd) in pmu_power_domain_st() argument
424 return mmio_read_32(PMU_BASE + PMU2_PWR_GATE_ST) & BIT(pd) ? in pmu_power_domain_st()
429 int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) in pmu_power_domain_ctr() argument
434 mmio_write_32(PMU_BASE + PMU2_PWR_GATE_SFTCON(pd / 16), in pmu_power_domain_ctr()
435 BITS_WITH_WMASK(pd_state, 0x1, pd % 16)); in pmu_power_domain_ctr()
438 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { in pmu_power_domain_ctr()
443 if (pmu_power_domain_st(pd) != pd_state) { in pmu_power_domain_ctr()
444 WARN("%s: %d, %d, (0x%x) error!\n", __func__, pd, pd_state, in pmu_power_domain_ctr()
/rk3399_ARM-atf/plat/imx/imx8ulp/xrdc/
H A Dxrdc_core.c186 uint16_t id, enum xrdc_pd_type pd) in xrdc_check_pd() argument
192 if (pd == XRDC_HIFI_PD) { in xrdc_check_pd()
195 } else if (pd == XRDC_AV_PD) { in xrdc_check_pd()
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c124 static inline uint32_t pmu_power_domain_st(uint32_t pd) in pmu_power_domain_st() argument
126 return mmio_read_32(PMU_BASE + PMU_PWRDN_ST) & BIT(pd) ? in pmu_power_domain_st()
131 static int pmu_power_domain_ctr(uint32_t pd, uint32_t pd_state) in pmu_power_domain_ctr() argument
139 BITS_WITH_WMASK(pd_state, 0x1, pd)); in pmu_power_domain_ctr()
142 while ((pmu_power_domain_st(pd) != pd_state) && (loop < PD_CTR_LOOP)) { in pmu_power_domain_ctr()
147 if (pmu_power_domain_st(pd) != pd_state) { in pmu_power_domain_ctr()
148 WARN("%s: %d, %d, error!\n", __func__, pd, pd_state); in pmu_power_domain_ctr()
/rk3399_ARM-atf/plat/brcm/board/stingray/src/
H A Dpaxb.c612 uint32_t nph, ph, pd; in paxb_cfg_pdl_ctrl() local
621 pd = PD_FC_INIT; in paxb_cfg_pdl_ctrl()
627 pd = SRP_PD_FC_INIT; in paxb_cfg_pdl_ctrl()
633 val = val | (pd << PD_FC_INIT_SHIFT); in paxb_cfg_pdl_ctrl()
/rk3399_ARM-atf/drivers/st/pmic/
H A Dstpmic2.c91 #define DEFINE_BUCK(regu_name, ID, pd, table) { \ argument
100 .pd_reg = pd, \
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/pmu/
H A Dpmu.c284 static inline void pll_pwr_dwn(uint32_t pll_id, uint32_t pd) in pll_pwr_dwn() argument
288 if (pd) in pll_pwr_dwn()
/rk3399_ARM-atf/docs/
H A Dchange-log.md6724 …- update ddr configure for ls1043ardb-pd ([18af644](https://review.trustedfirmware.org/plugins/git…