Searched refs:divn (Results 1 – 2 of 2) sorted by relevance
1199 uint32_t divn = vco->div_mn[PLL_CFG_N]; in clk_stm32_pll_compute_cfgr1() local1217 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_compute_cfgr1()1356 unsigned long long divn; in clk_compute_pll1_settings() local1362 divn = (freq / input_freq) - 1U; in clk_compute_pll1_settings()1363 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { in clk_compute_pll1_settings()1367 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); in clk_compute_pll1_settings()1378 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); in clk_compute_pll1_settings()1396 pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn; in clk_compute_pll1_settings()1706 uint32_t cfgr1, fracr, divm, divn; in clk_stm32_pll_recalc_rate() local1713 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_recalc_rate()[all …]
1049 uint32_t cfgr1, fracr, divm, divn; in stm32mp1_pll_get_fvco() local1056 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_get_fvco()1071 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; in stm32mp1_pll_get_fvco()1076 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); in stm32mp1_pll_get_fvco()1961 unsigned long long divn; in clk_compute_pll1_settings() local1967 divn = (freq / input_freq) - 1U; in clk_compute_pll1_settings()1968 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { in clk_compute_pll1_settings()1972 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); in clk_compute_pll1_settings()1983 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); in clk_compute_pll1_settings()1999 pllcfg[PLLCFG_N] = (uint32_t)divn; in clk_compute_pll1_settings()