Searched refs:divn (Results 1 – 2 of 2) sorted by relevance
1316 uint32_t divn = vco->div_mn[PLL_CFG_N]; in clk_stm32_pll_compute_cfgr1() local1334 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_compute_cfgr1()1473 unsigned long long divn; in clk_compute_pll1_settings() local1479 divn = (freq / input_freq) - 1U; in clk_compute_pll1_settings()1480 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { in clk_compute_pll1_settings()1484 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); in clk_compute_pll1_settings()1495 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); in clk_compute_pll1_settings()1513 pll1->vco.div_mn[PLL_CFG_N] = (uint32_t)divn; in clk_compute_pll1_settings()1961 uint32_t cfgr1, fracr, divm, divn; in clk_stm32_pll_recalc_rate() local1968 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_recalc_rate()[all …]
1049 uint32_t cfgr1, fracr, divm, divn; in stm32mp1_pll_get_fvco() local1056 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_get_fvco()1071 numerator = (((unsigned long long)divn + 1U) << 13) + fracv; in stm32mp1_pll_get_fvco()1076 fvco = (unsigned long)(refclk * (divn + 1U) / (divm + 1U)); in stm32mp1_pll_get_fvco()1970 unsigned long long divn; in clk_compute_pll1_settings() local1976 divn = (freq / input_freq) - 1U; in clk_compute_pll1_settings()1977 if ((divn < DIVN_MIN) || (divn > DIVN_MAX)) { in clk_compute_pll1_settings()1981 frac = ((freq * FRAC_MAX) / input_freq) - ((divn + 1U) * FRAC_MAX); in clk_compute_pll1_settings()1992 vco = (post_divm * (divn + 1U)) + ((post_divm * frac) / FRAC_MAX); in clk_compute_pll1_settings()2008 pllcfg[PLLCFG_N] = (uint32_t)divn; in clk_compute_pll1_settings()