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Searched refs:bl1_tzram_layout (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/qemu/common/
H A Dqemu_bl1_setup.c18 bl1_tzram_layout.total_base, \
19 bl1_tzram_layout.total_size, \
41 static meminfo_t bl1_tzram_layout; variable
46 return &bl1_tzram_layout; in bl1_plat_sec_mem_layout()
58 bl1_tzram_layout.total_base = BL_RAM_BASE; in bl1_early_platform_setup()
59 bl1_tzram_layout.total_size = BL_RAM_SIZE; in bl1_early_platform_setup()
/rk3399_ARM-atf/plat/rpi/rpi3/
H A Drpi3_bl1_setup.c22 static meminfo_t bl1_tzram_layout; variable
26 return &bl1_tzram_layout; in bl1_plat_sec_mem_layout()
52 bl1_tzram_layout.total_base = BL_RAM_BASE; in bl1_early_platform_setup()
53 bl1_tzram_layout.total_size = BL_RAM_SIZE; in bl1_early_platform_setup()
63 rpi3_setup_page_tables(bl1_tzram_layout.total_base, in bl1_plat_arch_setup()
64 bl1_tzram_layout.total_size, in bl1_plat_arch_setup()
/rk3399_ARM-atf/plat/hisilicon/poplar/
H A Dbl1_plat_setup.c29 static meminfo_t bl1_tzram_layout; variable
76 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
77 bl1_tzram_layout.total_size = BL1_RW_SIZE; in bl1_early_platform_setup()
85 plat_configure_mmu_el3(bl1_tzram_layout.total_base, in bl1_plat_arch_setup()
86 bl1_tzram_layout.total_size, in bl1_plat_arch_setup()
/rk3399_ARM-atf/plat/common/
H A Dplat_bl1_common.c83 meminfo_t *bl1_tzram_layout; in bl1_plat_handle_post_image_load() local
94 bl1_tzram_layout = bl1_plat_sec_mem_layout(); in bl1_plat_handle_post_image_load()
100 bl1_plat_calc_bl2_layout(bl1_tzram_layout, in bl1_plat_handle_post_image_load()
101 (meminfo_t *)bl1_tzram_layout->total_base); in bl1_plat_handle_post_image_load()
103 image_desc->ep_info.args.arg1 = (uintptr_t)bl1_tzram_layout->total_base; in bl1_plat_handle_post_image_load()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl1_setup.c30 static meminfo_t bl1_tzram_layout; variable
42 return &bl1_tzram_layout; in bl1_plat_sec_mem_layout()
55 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
56 bl1_tzram_layout.total_size = BL1_RW_SIZE; in bl1_early_platform_setup()
69 hikey_init_mmu_el3(bl1_tzram_layout.total_base, in bl1_plat_arch_setup()
70 bl1_tzram_layout.total_size, in bl1_plat_arch_setup()
/rk3399_ARM-atf/plat/arm/common/
H A Darm_bl1_setup.c37 bl1_tzram_layout.total_base, \
38 bl1_tzram_layout.total_size, \
62 static meminfo_t bl1_tzram_layout; variable
71 return &bl1_tzram_layout; in bl1_plat_sec_mem_layout()
89 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE; in arm_bl1_early_platform_setup()
90 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE; in arm_bl1_early_platform_setup()
326 bl1_plat_calc_bl2_layout(&bl1_tzram_layout,
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_bl1_setup.c43 static meminfo_t bl1_tzram_layout; variable
66 return &bl1_tzram_layout; in bl1_plat_sec_mem_layout()
87 bl1_tzram_layout.total_base = BL1_RW_BASE; in bl1_early_platform_setup()
88 bl1_tzram_layout.total_size = BL1_RW_SIZE; in bl1_early_platform_setup()
101 hikey960_init_mmu_el3(bl1_tzram_layout.total_base, in bl1_plat_arch_setup()
102 bl1_tzram_layout.total_size, in bl1_plat_arch_setup()