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/rk3399_ARM-atf/services/std_svc/spm/spm_mm/
H A Dspm_mm_xlat.c35 unsigned int access = (attributes & MM_SP_MEMORY_ATTRIBUTES_ACCESS_MASK) in smc_attr_to_mmap_attr() local
38 if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RW) { in smc_attr_to_mmap_attr()
40 } else if (access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_RO) { in smc_attr_to_mmap_attr()
44 assert(access == MM_SP_MEMORY_ATTRIBUTES_ACCESS_NOACCESS); in smc_attr_to_mmap_attr()
/rk3399_ARM-atf/include/lib/extensions/
H A Dras.h45 .access = ERR_ACCESS_SYSREG, \
54 .access = ERR_ACCESS_MEMMAP, \
157 unsigned int access:1; member
/rk3399_ARM-atf/docs/design/
H A Dalt-boot-flows.rst8 the highest exception level is required. It allows full, direct access to the
27 configured to permit secure access only. This gives full access to the whole
35 - Little-endian data access;
/rk3399_ARM-atf/docs/components/
H A Dsecure-partition-manager-mm.rst19 used by Non-secure world applications to access these services. A Trusted OS
46 privileged firmware (i.e. TF-A) to be granted access to system and processor
235 - Interfaces that enable access to privileged operations from S-EL0. These
236 operations typically require access to system resources that are either shared
255 Hence, the SVC conduit must be used by the Secure Partition to access interfaces
402 that it needs access to and their attributes. The SPM validates this resource
406 instruction access permissions.
408 2. Code memory regions are mapped with RO data and Executable instruction access
412 instruction access permissions.
415 instruction access permissions.
[all …]
H A Dnuma-per-cpu.rst14 memory, and CPUs within a node can access this memory with lower latency than
37 access across nodes incurs additional latency because of interconnect
39 nodes must access that data via the interconnect, leading to increased latency
45 framework optimizes the allocation and access of per-CPU objects by letting
46 platforms place them in the nodes with the lowest access latency.
84 CPUs access different addresses that lie on the same cache line. Although the
131 The NUMA-Aware Per-CPU Framework also provides macros to access per-CPU objects
215 visible to other CPUs or system components that may access this memory. This
H A Dgranule-protection-tables-design.rst13 address spaces have been added to control memory access for each state. The PAS
14 access allowed to each security state can be seen in the table below.
16 .. list-table:: Security states and PAS access rights
48 level 0 table controls access to a relatively large region in memory (GPT Block
111 structures, then the library will check the desired memory access layout for
153 During Granule Transition access to L1 tables is controlled by a lock to ensure
178 ``pas_region_t`` structures containing the desired memory access layout. The
H A Dffa-manifest-binding.rst279 - List of IDs belonging to a DMA capable peripheral device that has access to
285 - Identifies the SMMU IP that enforces the access control for the DMA device
288 - stream-ids-access-permissions
290 - List of attributes representing the instruction and data access permissions
291 used by the DMA device streams to access the memory region represented by
385 - exclusive-access
388 access and ownership of this device's MMIO region.
H A Ddebugfs-design.rst73 - This permits direct access to a firmware driver, mainly for test purposes
103 - On concurrent access, a spinlock is implemented in the BL31 service to protect
H A Dcontext-management-library.rst34 configuration of system registers independent of other security states to access
40 running in either state has the privileges to access them. Additionally, some of
51 unauthorized access or data corruption between the different security states.
134 - Any feature access which does not trap to EL3 should be symmetric.
181 #. ``context_el2.h`` : internal header consisting of helper macros to access EL2
556 Therefore, Root world should maintain its own distinct settings to access
565 Root Context needs to be setup as early as possible before we try and access/modify
/rk3399_ARM-atf/tools/fiptool/
H A Dwin_posix.h126 inline int access(const char *path, int mode) in access() function
/rk3399_ARM-atf/docs/plat/arm/tc/
H A Dindex.rst9 loaded by AP BL2 from FIP in flash to SRAM for copying by SCP (SCP has access
27 FIP to SRAM. The SCP has access to AP SRAM. The address and size of SCP_BL2
/rk3399_ARM-atf/docs/threat_model/firmware_threat_model/
H A Dthreat_model_rse_interface.rst47 - ID 11: The access to the communication interface between AP and RSE is
50 gain access to sensitive data.
H A Dthreat_model.rst77 | DF3 | | Debug and trace IP on a platform can allow access |
152 | AppDebug | | Physical attacker using debug signals to access |
155 | PhysicalAccess | | Physical attacker having access to external device |
263 that require physical access are unlikely in server environments while
461 | | access memory beyond its limit. |
490 | | access sensitive data, execute arbitrary |
491 | | code or access otherwise restricted HW |
496 | | normal world to access sensitive data or even |
519 | Mitigations | When configuring access permissions, the |
549 | | gains access to memory due to a vulnerability. |
[all …]
H A Dthreat_model_el3_spm.rst66 | DF7 | External memory access. |
113 - Hardware attacks (non-invasive) requiring a physical access to the device,
335 | | getting access or gaining permissions to a memory |
535 | | access this service.** |
600 | | be able to relinquish the access to shared memory |
638 | Mitigations | Yes. The SPMC tracks ownership and access state |
/rk3399_ARM-atf/plat/nvidia/tegra/include/t186/
H A Dtegra_mc_def.h334 #define mc_make_sec_cfg(off, ns, ovrrd, access) \ argument
341 .override_enable = OVERRIDE_ ## access \
/rk3399_ARM-atf/docs/plat/marvell/armada/misc/
H A Dmvebu-io-win.rst14 - **0x2** = SPI direct access
/rk3399_ARM-atf/docs/security_advisories/
H A Dsecurity-advisory-tfv-3.rst29 contains flags to control data access permissions (``MT_RO``/``MT_RW``) and
47 permissions separately to data access permissions. All RO normal memory regions
H A Dsecurity-advisory-tfv-11.rst51 register. Which may cause a data abort or an access to a random EL3 memory region.
/rk3399_ARM-atf/fdts/
H A Dstmm_template.dts28 * System registers, rtc, uart and etc regions for access from S-EL0.
/rk3399_ARM-atf/docs/design_documents/
H A Ddtpm_drivers.rst38 such as getting information, requesting access, and relinquishing access,
H A Drse.rst61 - ``Pointer-access messaging``: The message header and the payload are
70 ``iovec``. Therefore, the sender must handle both cases and prevent access to
87 V | |access | |
192 | Register access | IRQ
205 | IRQ | Register access
439 it on behalf of RMM. The access to MHU interface and thereby to RSE is
440 restricted to BL31 only. Therefore, RMM does not have direct access, all calls
742 RSE provides access for AP to assets in OTP, which include keys for image
/rk3399_ARM-atf/docs/getting_started/
H A Dbuild-options.rst314 extension. It allows access to the SCXTNUM_EL2 (Software Context Number)
340 Virtualization feature, allowing for access to the CNTPOFF_EL2 (Counter-timer
347 Mode Register feature, allowing access to the FPMR register. FPMR register
353 feature allowing for access to the HDFGRTR_EL2 (Hypervisor Debug Fine-Grained
360 (Fine Grain Traps 2) feature allowing for access to Fine-grained trap 2 registers
376 This feature currently traps access to all EL3 registers in
384 allow access to HCRX_EL2 (extended hypervisor control register) from EL2 as
420 permission fault for any privileged data access from EL1/EL2 to virtual
463 Host Extensions) extension. It allows access to CONTEXTIDR_EL2 register
470 allow access t
[all...]
/rk3399_ARM-atf/plat/arm/board/neoverse_rd/platform/rdn2/fdts/
H A Drdn2_stmm_sel0_manifest.dts48 * System registers region for access from S-EL0.
/rk3399_ARM-atf/docs/plat/arm/
H A Darm-build-options.rst13 - ``ARM_CONFIG_CNTACR``: boolean option to unlock access to the ``CNTBase<N>``
17 kernel). Default is true (access to the frame is allowed).
46 MPIDR is set and access the bit-fields in MPIDR accordingly. Default value of
/rk3399_ARM-atf/docs/plat/
H A Drz-g2.rst82 behind using direct shared memory access to BOOT_KIND_BASE _and_
162 - Boot the board in Mini-monitor mode and enable access to the

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