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/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.h224 #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ argument
227 .parent = (_parent),\
239 #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ argument
242 .parent = (_parent),\
258 #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ argument
261 .parent = (_parent),\
269 #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ argument
272 .parent = (_parent),\
295 #define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ argument
298 .parent = (_parent),\
[all …]
H A Dclk-stm32mp2.c914 #define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ argument
916 .parent = _parent,\
962 #define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ argument
964 .parent = _parent,\
1140 #define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \ argument
1143 .parent = (_parent),\
1157 #define CLK_RTC(idx, _binding, _parent, _flags, _gate_id)[idx] = {\ argument
1159 .parent = (_parent),\
H A Dclk-stm32mp13.c1771 #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ argument
1773 .parent = _parent,\
1826 #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ argument
1829 .parent = (_parent),\