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/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32-core.h216 #define STM32_DIV(idx, _binding, _parent, _flags, _div_id) \ argument
219 .parent = (_parent),\
231 #define STM32_GATE(idx, _binding, _parent, _flags, _gate_id) \ argument
234 .parent = (_parent),\
250 #define FIXED_FACTOR(idx, _idx, _parent, _mult, _div) \ argument
253 .parent = (_parent),\
261 #define GATE(idx, _binding, _parent, _flags, _offset, _bit_idx) \ argument
264 .parent = (_parent),\
287 #define CK_TIMER(idx, _idx, _parent, _flags, _apbdiv, _timpre) \ argument
290 .parent = (_parent),\
H A Dclk-stm32mp2.c1154 #define CLK_PLL(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ argument
1156 .parent = _parent,\
1202 #define CLK_PLL1(idx, _idx, _parent, _pll_id, _flags)[idx] = {\ argument
1204 .parent = _parent,\
1380 #define CLK_OSC(idx, _idx, _parent, _osc_id) \ argument
1383 .parent = (_parent),\
1391 #define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ argument
1394 .parent = (_parent),\
1402 #define CLK_OSC_MSI(idx, _idx, _parent, _osc_id) \ argument
1405 .parent = (_parent),\
[all …]
H A Dclk-stm32mp13.c1909 #define CLK_OSC(idx, _idx, _parent, _osc_id) \ argument
1912 .parent = (_parent),\
1920 #define CLK_OSC_FIXED(idx, _idx, _parent, _osc_id) \ argument
1923 .parent = (_parent),\
2026 #define CLK_PLL(idx, _idx, _parent, _gate, _pll_id, _flags)[idx] = {\ argument
2028 .parent = _parent,\
2081 #define STM32_COMPOSITE(idx, _binding, _parent, _flags, _gate_id,\ argument
2084 .parent = (_parent),\