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Searched refs:VPPSYS0_SW_CG0 (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_cond.c38 #define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020) macro
97 IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/
H A Dmt_spm_cond.c41 #define VPPSYS0_SW_CG0 MT_LP_TZ_VPPSYS0_REG(0x0020) macro
103 IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),