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Searched refs:VCP_R_SEC_CTRL (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/vcp/mt8196/
H A Dvcp_reg.h56 #define VCP_R_SEC_CTRL (MTK_VCP_REG_BASE + 0x270000) macro
59 #define VCP_R_SEC_CTRL_2 (VCP_R_SEC_CTRL + 0x0004)
62 #define VCP_GPR0_CFGREG_SEC (VCP_R_SEC_CTRL + 0x0040)
63 #define VCP_GPR1_CFGREG_SEC (VCP_R_SEC_CTRL + 0x0044)
64 #define VCP_GPR2_CFGREG_SEC (VCP_R_SEC_CTRL + 0x0048)
65 #define VCP_GPR3_CFGREG_SEC (VCP_R_SEC_CTRL + 0x004C)
66 #define VCP_R_SEC_DOMAIN (VCP_R_SEC_CTRL + 0x0080)
80 #define VCP_R_SEC_DOMAIN_MMPC (VCP_R_SEC_CTRL + 0x0084)
85 #define R_L2TCM_OFFSET_RANGE_0_LOW (VCP_R_SEC_CTRL + 0x00B0)
86 #define R_L2TCM_OFFSET_RANGE_0_HIGH (VCP_R_SEC_CTRL + 0x00B4)
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/rk3399_ARM-atf/plat/mediatek/drivers/vcp/rv/
H A Dmmup_common.c75 mmio_setbits_32(VCP_R_SEC_CTRL, VCP_OFFSET_ENABLE_P | VCP_OFFSET_ENABLE_B); in mmup_smc_rstn_clr()
H A Dvcp_common.c33 MAP_REGION_FLAT(VCP_R_SEC_CTRL, MTK_VCP_REG_BANK_SIZE,