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Searched refs:SPM_MP0_CPUTOP_PWR_CON (Results 1 – 10 of 10) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/
H A Dmtspmc_private.h69 #define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204) macro
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
H A Dmtspmc.c110 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc_private.h67 #define SPM_MP0_CPUTOP_PWR_CON SPM_REG(0x204) macro
93 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
H A Dmtspmc.c107 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/
H A Dmtspmc_private.h69 #define SPM_MP0_CPUTOP_PWR_CON MCUCFG_REG(0xd204) macro
95 { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON, .cpu_stride = 0U }
H A Dmtspmc.c102 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in spmc_init()
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spmc/
H A Dmtspmc_private.h35 #define SPM_MP0_CPUTOP_PWR_CON (SPM_BASE + 0x204) macro
113 [0] = { .cluster_addr = SPM_MP0_CPUTOP_PWR_CON },
/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_smp.c114 mmio_clrbits_32(SPM_MP0_CPUTOP_PWR_CON, RESETPWRON_CONFIG); in mt_smp_init()
/rk3399_ARM-atf/plat/mediatek/drivers/mcusys/v1/
H A Dmcucfg.h70 #define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xD204) macro
/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v1/
H A Dmcucfg.h124 #define SPM_MP0_CPUTOP_PWR_CON (MCUCFG_BASE + 0xd204) macro