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Searched refs:SPM2SW_MAILBOX_0 (Results 1 – 11 of 11) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8189/
H A Dmt_spm_idle.c389 mmio_write_32(SPM2SW_MAILBOX_0, 0x1); in mt_spm_idle_generic_enter()
414 mmio_write_32(SPM2SW_MAILBOX_0, 0x0); in mt_spm_idle_generic_resume()
H A Dmt_spm_suspend.c433 mmio_write_32(SPM2SW_MAILBOX_0, 0x1); in mt_spm_suspend_enter()
475 mmio_write_32(SPM2SW_MAILBOX_0, 0x0); in mt_spm_suspend_resume()
H A Dmt_spm_reg.h75 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x240) macro
/rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8196/
H A Dmt_spm_idle.c564 mmio_write_32(SPM2SW_MAILBOX_0, 0x1); in mt_spm_idle_generic_enter()
593 mmio_write_32(SPM2SW_MAILBOX_0, 0x0); in mt_spm_idle_generic_resume()
H A Dmt_spm_suspend.c628 mmio_write_32(SPM2SW_MAILBOX_0, 0x1); in mt_spm_suspend_enter()
671 mmio_write_32(SPM2SW_MAILBOX_0, 0x0); in mt_spm_suspend_resume()
H A Dmt_spm_reg.h77 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x0240) macro
/rk3399_ARM-atf/plat/mediatek/mt8188/include/
H A Dspm_reg.h148 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) macro
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/
H A Dmt_spm_reg.h144 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) macro
/rk3399_ARM-atf/plat/mediatek/mt8183/drivers/spm/
H A Dspm.h268 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x5D0) macro
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/
H A Dmt_spm_reg.h160 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/
H A Dmt_spm_reg.h163 #define SPM2SW_MAILBOX_0 (SPM_BASE + 0x2D0) macro