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Searched refs:SCU_CPU_DPLL (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/aspeed/ast2700/include/
H A Dplatform_reg.h24 #define SCU_CPU_DPLL (SCU_CPU_BASE + 0x308) macro
/rk3399_ARM-atf/plat/aspeed/ast2700/
H A Dplat_bl31_setup.c151 pll_reg.w = mmio_read_32(SCU_CPU_DPLL); in plat_get_pll_rate()