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Searched refs:SCRU_BASE (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/scmi/
H A Drk3588_clk.c1177 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x3000; in clk_scmi_cclk_sdmmc_get_rate()
1179 div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0fc0; in clk_scmi_cclk_sdmmc_get_rate()
1196 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), in clk_scmi_cclk_sdmmc_set_rate()
1201 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), in clk_scmi_cclk_sdmmc_set_rate()
1206 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), in clk_scmi_cclk_sdmmc_set_rate()
1216 mmio_write_32(SCRU_BASE + CRU_CLKGATE_CON(3), in clk_scmi_cclk_sdmmc_set_status()
1226 src = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x0020; in clk_scmi_dclk_sdmmc_get_rate()
1227 div = mmio_read_32(SCRU_BASE + CRU_CLKSEL_CON(3)) & 0x001f; in clk_scmi_dclk_sdmmc_get_rate()
1241 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), in clk_scmi_dclk_sdmmc_set_rate()
1246 mmio_write_32(SCRU_BASE + CRU_CLKSEL_CON(3), in clk_scmi_dclk_sdmmc_set_rate()
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H A Drk3588_rstd.c36 mmio_write_32(SCRU_BASE + CRU_SOFTRST_CON(bank), in rk3588_reset_explicit()
/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/otp/
H A Dotp.c67 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01); in enable_otp_clk()
69 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in enable_otp_clk()
74 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01); in enable_otp_clk()
76 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in enable_otp_clk()
81 reg = mmio_read_32(SCRU_BASE + SCRU_GATE_CON01); in enable_otp_clk()
83 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in enable_otp_clk()
119 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in restore_otp_clk()
124 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in restore_otp_clk()
129 mmio_write_32(SCRU_BASE + SCRU_GATE_CON01, in restore_otp_clk()
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h39 #define SCRU_BASE 0xfdd10000 macro
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpm_pd_regs.c103 REG_REGION(0x300, 0x30c, 4, SCRU_BASE, WMSK_VAL),
104 REG_REGION(0x800, 0x80c, 4, SCRU_BASE, WMSK_VAL),
105 REG_REGION(0xa00, 0xa0c, 4, SCRU_BASE, WMSK_VAL),
106 REG_REGION(0xd00, 0xd20, 8, SCRU_BASE, 0),
107 REG_REGION(0xd04, 0xd24, 8, SCRU_BASE, WMSK_VAL),
H A Dpmu.c207 clk_save[j] = mmio_read_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i)); in clk_gate_con_save()
223 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), 0xffff0000); in clk_gate_con_disable()
241 mmio_write_32(SCRU_BASE + SECURECRU_CLKGATE_CON(i), in clk_gate_con_restore()
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h66 #define SCRU_BASE 0xfd7d0000 macro