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Searched refs:S32CC_DDR_PLL_PHI0_FREQ (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_early_clks.c22 #define S32CC_DDR_PLL_PHI0_FREQ (800U * MHZ) macro
164 ret = clk_set_rate(S32CC_CLK_DDR_PLL_PHI0, S32CC_DDR_PLL_PHI0_FREQ, NULL); in setup_ddr_pll()