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Searched refs:S32CC_CLK_MC_CGM5_MUX0 (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/drivers/nxp/clk/s32cc/
H A Ds32cc_early_clks.c176 ret = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_DDR_PLL_PHI0); in enable_ddr_clk()
224 err = clk_set_parent(S32CC_CLK_MC_CGM5_MUX0, S32CC_CLK_FIRC); in plat_deassert_ddr_reset()
H A Ds32cc_clk_modules.c255 [S32CC_CLK_ID(S32CC_CLK_MC_CGM5_MUX0)] = &cgm5_mux0_clk,
/rk3399_ARM-atf/include/drivers/nxp/clk/s32cc/
H A Ds32cc-clk-ids.h103 #define S32CC_CLK_MC_CGM5_MUX0 S32CC_ARCH_CLK(20) macro