Searched refs:S32CC_CLK_MC_CGM1_MUX0 (Results 1 – 3 of 3) sorted by relevance
76 #define S32CC_CLK_MC_CGM1_MUX0 S32CC_ARCH_CLK(2) macro
88 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); in enable_a53_clk()
243 [S32CC_CLK_ID(S32CC_CLK_MC_CGM1_MUX0)] = &cgm1_mux0_clk,