Searched refs:S32CC_CLK_ARM_PLL_PHI0 (Results 1 – 3 of 3) sorted by relevance
54 ret = clk_set_rate(S32CC_CLK_ARM_PLL_PHI0, S32CC_ARM_PLL_PHI0_FREQ, NULL); in setup_arm_pll()88 ret = clk_set_parent(S32CC_CLK_MC_CGM1_MUX0, S32CC_CLK_ARM_PLL_PHI0); in enable_a53_clk()
113 S32CC_CLK_ARM_PLL_PHI0,207 [S32CC_CLK_ID(S32CC_CLK_ARM_PLL_PHI0)] = &arm_pll_phi0_clk,
32 #define S32CC_CLK_ARM_PLL_PHI0 S32CC_HW_CLK(4) macro