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Searched refs:RK3568_CLK_SEL (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3568/drivers/scmi/
H A Drk3568_clk.c297 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), in rk3568_apll_set_rate()
388 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), in clk_cpu_set_rate()
390 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(1), in clk_cpu_set_rate()
393 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(3), in clk_cpu_set_rate()
396 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(4), in clk_cpu_set_rate()
400 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), CLKDIV_4BITS_SHF0(3)); in clk_cpu_set_rate()
403 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), CPU_CLK_PATH_NOR_GPLL); in clk_cpu_set_rate()
405 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(2), SCLK_PATH_NOR_GPLL); in clk_cpu_set_rate()
413 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(0), CLK_CORE_PATH_DIR_APLL); in clk_cpu_set_rate()
418 mmio_write_32(CRU_BASE + RK3568_CLK_SEL(3), in clk_cpu_set_rate()
[all …]
H A Drk3568_clk.h57 #define RK3568_CLK_SEL(x) ((x) * 0x4 + 0x100) macro