Searched refs:RCC_PLLxCFGR6_POSTDIV1_MASK (Results 1 – 3 of 3) sorted by relevance
891 postdiv1 = mmio_read_32(pllxcfgr6) & RCC_PLLxCFGR6_POSTDIV1_MASK; in clk_stm32_pll_recalc_rate()1679 mmio_clrsetbits_32(pllxcfgr6, RCC_PLLxCFGR6_POSTDIV1_MASK, in clk_stm32_pll_config_output()1680 pllcfg[POSTDIV1] & RCC_PLLxCFGR6_POSTDIV1_MASK); in clk_stm32_pll_config_output()
2852 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) macro4655 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) macro
3048 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) macro4975 #define RCC_PLLxCFGR6_POSTDIV1_MASK GENMASK_32(2, 0) macro