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Searched refs:RCC_PLLxCFGR5_DIVVAL_MASK (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp2.c1706 mmio_clrsetbits_32(pllxcfgr5, RCC_PLLxCFGR5_DIVVAL_MASK, in clk_stm32_pll_config_csg()
1707 csg[DIVVAL] & RCC_PLLxCFGR5_DIVVAL_MASK); in clk_stm32_pll_config_csg()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp21_rcc.h2846 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) macro
4649 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) macro
H A Dstm32mp25_rcc.h3042 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) macro
4969 #define RCC_PLLxCFGR5_DIVVAL_MASK GENMASK_32(3, 0) macro