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Searched refs:RCC_PLLNCFGR1_DIVN_SHIFT (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c1764 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & in stm32mp1_check_pll_conf()
1895 value = (pllcfg[PLLCFG_N] << RCC_PLLNCFGR1_DIVN_SHIFT) & in stm32mp1_pll_config()
H A Dclk-stm32mp13.c1217 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_compute_cfgr1()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h1764 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 macro
H A Dstm32mp15_rcc.h2291 #define RCC_PLLNCFGR1_DIVN_SHIFT 0 macro