Searched refs:RCC_PLLNCFGR1_DIVN_MASK (Results 1 – 4 of 4) sorted by relevance
1056 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_get_fvco()1765 RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_check_pll_conf()1896 RCC_PLLNCFGR1_DIVN_MASK; in stm32mp1_pll_config()
1217 *value |= (divn << RCC_PLLNCFGR1_DIVN_SHIFT) & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_compute_cfgr1()1713 divn = cfgr1 & RCC_PLLNCFGR1_DIVN_MASK; in clk_stm32_pll_recalc_rate()
1765 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) macro
2290 #define RCC_PLLNCFGR1_DIVN_MASK GENMASK(8, 0) macro