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Searched refs:RCC_DDRITFCR (Results 1 – 7 of 7) sorted by relevance

/rk3399_ARM-atf/drivers/st/ddr/
H A Dstm32mp1_ddr.c588 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
589 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAXIRST); in stm32mp1_ddr_init()
590 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
591 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYAPBRST); in stm32mp1_ddr_init()
592 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
593 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
602 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYRST); in stm32mp1_ddr_init()
603 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DPHYCTLRST); in stm32mp1_ddr_init()
608 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST); in stm32mp1_ddr_init()
650 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCORERST); in stm32mp1_ddr_init()
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H A Dstm32mp1_ddr_helpers.c16 mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR, in ddr_enable_clock()
H A Dstm32mp1_ram.c93 mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); in stm32mp1_ddr_setup()
98 mmio_setbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN); in stm32mp1_ddr_setup()
/rk3399_ARM-atf/drivers/st/clk/
H A Dstm32mp1_clk.c589 _CLK_FIXED(SEC, RCC_DDRITFCR, 0, DDRC1, _ACLK),
590 _CLK_FIXED(SEC, RCC_DDRITFCR, 1, DDRC1LP, _ACLK),
591 _CLK_FIXED(SEC, RCC_DDRITFCR, 2, DDRC2, _ACLK),
592 _CLK_FIXED(SEC, RCC_DDRITFCR, 3, DDRC2LP, _ACLK),
593 _CLK_FIXED(SEC, RCC_DDRITFCR, 4, DDRPHYC, _PLL2_R),
594 _CLK_FIXED(SEC, RCC_DDRITFCR, 5, DDRPHYCLP, _PLL2_R),
595 _CLK_FIXED(SEC, RCC_DDRITFCR, 6, DDRCAPB, _PCLK4),
596 _CLK_FIXED(SEC, RCC_DDRITFCR, 7, DDRCAPBLP, _PCLK4),
597 _CLK_FIXED(SEC, RCC_DDRITFCR, 8, AXIDCG, _ACLK),
598 _CLK_FIXED(SEC, RCC_DDRITFCR, 9, DDRPHYCAPB, _PCLK4),
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H A Dclk-stm32mp13.c639 GATE_CFG(GATE_DDRC1, RCC_DDRITFCR, 0, 0),
640 GATE_CFG(GATE_DDRC1LP, RCC_DDRITFCR, 1, 0),
641 GATE_CFG(GATE_DDRPHYC, RCC_DDRITFCR, 4, 0),
642 GATE_CFG(GATE_DDRPHYCLP, RCC_DDRITFCR, 5, 0),
643 GATE_CFG(GATE_DDRCAPB, RCC_DDRITFCR, 6, 0),
644 GATE_CFG(GATE_DDRCAPBLP, RCC_DDRITFCR, 7, 0),
645 GATE_CFG(GATE_AXIDCG, RCC_DDRITFCR, 8, 0),
646 GATE_CFG(GATE_DDRPHYCAPB, RCC_DDRITFCR, 9, 0),
647 GATE_CFG(GATE_DDRPHYCAPBLP, RCC_DDRITFCR, 10, 0),
2099 mmio_clrsetbits_32(priv->base + RCC_DDRITFCR, in stm32mp1_init_clock_tree()
/rk3399_ARM-atf/include/drivers/st/
H A Dstm32mp13_rcc.h76 #define RCC_DDRITFCR U(0X5C0) macro
H A Dstm32mp15_rcc.h42 #define RCC_DDRITFCR U(0xD8) macro