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Searched refs:PLL_NORMAL_MODE (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Dmisc_regs.h20 #define PLL_NORMAL_MODE 1 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/pmu/
H A Dplat_pmu_macros.S31 #define PLL_NORMAL_MODE ((0x3 << (PLL_MODE_SHIFT + 16)) | \ macro
48 ldr w6, =(PLL_NORMAL_MODE)
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/m0/src/
H A Ddram.c55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()