Searched refs:PLL_MODE (Results 1 – 3 of 3) sorted by relevance
43 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE)); in ddr_set_pll()55 mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE)); in ddr_set_pll()
21 #define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8)) macro
19 enum pll_set_rate_mode PLL_MODE = CON0_PCW; variable251 anpu_pll_set_rate(domain, PLL_MODE, (div2) ? (freq * 2) : freq); in apupwr_smc_pll_set_rate()