Searched refs:OFFSET_DFIPHYMSTR (Results 1 – 2 of 2) sorted by relevance
164 mmio_clrbits_32(DDRC_BASE + OFFSET_DFIPHYMSTR, DFIPHYMSTR_ENABLE); in post_train_setup()167 err = mmio_read_32_poll_timeout(DDRC_BASE + OFFSET_DFIPHYMSTR, phymstr_reg, in post_train_setup()223 mmio_setbits_32(DDRC_BASE + OFFSET_DFIPHYMSTR, DFIPHYMSTR_ENABLE); in post_train_setup()226 err = mmio_read_32_poll_timeout(DDRC_BASE + OFFSET_DFIPHYMSTR, phymstr_reg, in post_train_setup()
196 #define OFFSET_DFIPHYMSTR 0x1C4U macro