Searched refs:MVEBU_PM_NB_PWR_OPTION_REG (Results 1 – 1 of 1) sorted by relevance
82 #define MVEBU_PM_NB_PWR_OPTION_REG (MVEBU_PMSU_REG_BASE + 0x8) macro313 mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_CPU_VDDV_OFF_EN); in a3700_set_gen_pwr_off_option()337 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_NB_SRAM_LKG_PD_EN); in a3700_set_gen_pwr_off_option()383 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_SR_EN); in a3700_en_ddr_self_refresh()385 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDR_CLK_DIS_EN); in a3700_en_ddr_self_refresh()387 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_DDRPHY_PWRDWN_EN); in a3700_en_ddr_self_refresh()388 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, in a3700_en_ddr_self_refresh()415 mmio_clrbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_AVS_DISABLE_MODE); in a3700_pwr_dn_avs()422 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_AVS_VDD2_MODE); in a3700_pwr_dn_avs()423 mmio_setbits_32(MVEBU_PM_NB_PWR_OPTION_REG, MVEBU_PM_AVS_HOLD_MODE); in a3700_pwr_dn_avs()[all …]