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Searched refs:MVEBU_DRAM_CH0_CMD0 (Results 1 – 1 of 1) sorted by relevance

/rk3399_ARM-atf/plat/marvell/armada/a3k/common/
H A Dplat_pm.c165 #define MVEBU_DRAM_CH0_CMD0 BIT(28) macro
396 mmio_write_32(MVEBU_DRAM_CMD_0_REG, MVEBU_DRAM_CH0_CMD0 | in a3700_en_ddr_self_refresh()