| /rk3399_ARM-atf/drivers/nxp/clk/s32cc/include/ |
| H A D | s32cc-clk-regs.h | 74 #define CGM_MUXn_CSC(CGM_ADDR, MUX) ((CGM_ADDR) + 0x300UL + ((MUX) * 0x40UL)) argument
82 #define CGM_MUXn_CSS(CGM_ADDR, MUX) ((CGM_ADDR) + 0x304UL + ((MUX) * 0x40UL)) argument
96 #define MC_CGM_MUXn_DCm(CGM_ADDR, MUX, DC) \ argument
98 ((MUX) * 0x40UL) + ((DC) * 0x4UL))
106 #define MC_CGM_MUXn_DIV_UPD_STAT(CGM_ADDR, MUX) \ argument
107 (((CGM_ADDR) + 0x33CUL + ((MUX) * 0x40UL)))
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| /rk3399_ARM-atf/drivers/st/clk/ |
| H A D | clk-stm32mp13.c | 1879 CLK_PLL(_CK_PLL1, PLL1, MUX(MUX_PLL12), GATE_PLL1, _PLL1, 0),
1880 CLK_PLL(_CK_PLL2, PLL2, MUX(MUX_PLL12), GATE_PLL2, _PLL2, 0),
1881 CLK_PLL(_CK_PLL3, PLL3, MUX(MUX_PLL3), GATE_PLL3, _PLL3, 0),
1882 CLK_PLL(_CK_PLL4, PLL4, MUX(MUX_PLL4), GATE_PLL4, _PLL4, 0),
1900 STM32_DIV(_CKAXI, CK_AXI, MUX(MUX_AXI), 0, DIV_AXI),
1901 STM32_DIV(_CKMLAHB, CK_MLAHB, MUX(MUX_MLAHB), CLK_IS_CRITICAL, DIV_MLAHB),
1902 STM32_MUX(_CKPER, CK_PER, MUX(MUX_CKPER), 0),
1930 STM32_GATE(_USBPHY_K, USBPHY_K, MUX(MUX_USBPHY), 0, GATE_USBPHY),
1931 STM32_GATE(_USBO_K, USBO_K, MUX(MUX_USBO), 0, GATE_USBO),
1938 STM32_GATE(_STGENC, STGEN_K, MUX(MUX_STGEN), CLK_IS_CRITICAL, GATE_STGENC),
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| H A D | clk-stm32-core.h | 133 #define MUX(mux) ((mux) | MUX_FLAG) macro
284 .parent = (MUX(_mux_id)),\
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| H A D | clk-stm32mp2.c | 1074 .parent = MUX(MUX_XBARSEL),\
1211 CLK_RTC(_CK_RTCCK, RTC_CK, MUX(MUX_RTC), 0, GATE_RTCCK),
1213 CLK_PLL1(_CK_PLL1, PLL1_CK, MUX(MUX_MUXSEL5), _PLL1, 0),
1215 CLK_PLL(_CK_PLL2, PLL2_CK, MUX(MUX_MUXSEL6), _PLL2, 0),
1217 CLK_PLL(_CK_PLL3, PLL3_CK, MUX(MUX_MUXSEL7), _PLL3, 0),
1219 CLK_PLL(_CK_PLL4, PLL4_CK, MUX(MUX_MUXSEL0), _PLL4, 0),
1220 CLK_PLL(_CK_PLL5, PLL5_CK, MUX(MUX_MUXSEL1), _PLL5, 0),
1221 CLK_PLL(_CK_PLL6, PLL6_CK, MUX(MUX_MUXSEL2), _PLL6, 0),
1222 CLK_PLL(_CK_PLL7, PLL7_CK, MUX(MUX_MUXSEL3), _PLL7, 0),
1223 CLK_PLL(_CK_PLL8, PLL8_CK, MUX(MUX_MUXSEL4), _PLL8, 0),
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