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Searched refs:MCUSYS_CPC_BASE (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v2/
H A Dmcucfg.h15 #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000) macro
18 #define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
19 #define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
20 #define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
21 #define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
22 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
23 #define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
24 #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
25 #define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
26 #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
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/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v3/
H A Dmcucfg.h15 #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000) macro
18 #define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
19 #define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
20 #define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
21 #define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
22 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
23 #define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
24 #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
25 #define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
26 #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
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/rk3399_ARM-atf/plat/mediatek/include/drivers/mcusys/v4/
H A Dmcucfg.h15 #define MCUSYS_CPC_BASE (MCUCFG_BASE + 0x40000) macro
18 #define CPC_FCM_SPMC_SW_CFG2 (MCUSYS_CPC_BASE + 0x004)
19 #define CPC_FCM_SPMC_PWR_STATUS (MCUSYS_CPC_BASE + 0x010)
20 #define CPC_MCUSYS_CPC_OFF_THRES (MCUSYS_CPC_BASE + 0x014)
21 #define CPC_MCUSYS_PWR_CTRL (MCUSYS_CPC_BASE + 0x104)
22 #define CPC_MCUSYS_CPC_FLOW_CTRL_CFG (MCUSYS_CPC_BASE + 0x114)
23 #define CPC_MCUSYS_LAST_CORE_REQ (MCUSYS_CPC_BASE + 0x118)
24 #define CPC_MCUSYS_MP_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x11c)
25 #define CPC_MCUSYS_LAST_CORE_RESP (MCUSYS_CPC_BASE + 0x124)
26 #define CPC_MCUSYS_PWR_ON_MASK (MCUSYS_CPC_BASE + 0x128)
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