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Searched refs:MCUCFG_MP0_CLUSTER_CFG5 (Results 1 – 4 of 4) sorted by relevance

/rk3399_ARM-atf/plat/mediatek/drivers/cpu_pm/cpcv3_2/
H A Dmt_cpu_pm.h51 ctrl.arch_addr = MCUCFG_MP0_CLUSTER_CFG5; \
101 #define MCUCFG_MP0_CLUSTER_CFG5 (MCUCFG_BASE + 0xc8e4) macro
/rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spmc/
H A Dmtspmc_private.h100 #define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4) macro
121 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
/rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spmc/
H A Dmtspmc_private.h97 #define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4) macro
115 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }
/rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spmc/
H A Dmtspmc_private.h100 #define MCUCFG_MP0_CLUSTER_CFG5 MCUCFG_REG(0xc8e4) macro
121 { .cluster_addr = MCUCFG_MP0_CLUSTER_CFG5, .cpu_stride = 0U }