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Searched refs:IMX_CGC2_BASE (Results 1 – 2 of 2) sorted by relevance

/rk3399_ARM-atf/plat/imx/imx8ulp/
H A Ddram.c574 while (mmio_read_32(IMX_CGC2_BASE + 0x40) & BIT(31)) in set_cgc2_ddrclk()
577 mmio_write_32(IMX_CGC2_BASE + 0x40, (src << 28) | (div << 21)); in set_cgc2_ddrclk()
579 while (!(mmio_read_32(IMX_CGC2_BASE + 0x40) & BIT(27))) in set_cgc2_ddrclk()
611 while (mmio_read_32(IMX_CGC2_BASE + 0x40) & BIT(31)) { in set_ddr_clk()
/rk3399_ARM-atf/plat/imx/imx8ulp/include/
H A Dplatform_def.h73 #define IMX_CGC2_BASE U(0x2da60000) macro