| /rk3399_ARM-atf/plat/mediatek/mt8195/drivers/spm/ |
| H A D | mt_spm_cond.c | 86 #define IDLE_CG(mask, addr, bitflip, clkmux) \ macro
90 IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
91 IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0U),
92 IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0U),
93 IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0U),
94 IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0U),
95 IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0U),
96 IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0U),
97 IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK|CLKMUX_DISP)),
98 IDLE_CG(0x00000800, VPPSYS0_SW_CG1, true, (CLK_CHECK|CLKMUX_DISP)),
[all …]
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| /rk3399_ARM-atf/plat/mediatek/drivers/spm/mt8188/ |
| H A D | mt_spm_cond.c | 92 #define IDLE_CG(mask, addr, bitflip, clkmux) {mask, (uintptr_t)addr, bitflip, clkmux} macro
95 IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0),
96 IDLE_CG(0xffffffff, SPM_CPU_PWR_STATUS, false, 0),
97 IDLE_CG(0xffffffff, INFRA_SW_CG0, true, 0),
98 IDLE_CG(0xffffffff, INFRA_SW_CG1, true, 0),
99 IDLE_CG(0xffffffff, INFRA_SW_CG2, true, 0),
100 IDLE_CG(0xffffffff, INFRA_SW_CG3, true, 0),
101 IDLE_CG(0xffffffff, INFRA_SW_CG4, true, 0),
102 IDLE_CG(0xffffffff, PERI_SW_CG0, true, 0),
103 IDLE_CG(0x00000800, VPPSYS0_SW_CG0, true, (CLK_CHECK | CLKMUX_VPP)),
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8186/drivers/spm/ |
| H A D | mt_spm_cond.c | 74 #define IDLE_CG(mask, addr, bitflip, clkmux) \ macro
78 IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
79 IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U),
80 IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U),
81 IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U),
82 IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U),
83 IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U),
84 IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U),
85 IDLE_CG(0x00200000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)),
86 IDLE_CG(0x00200000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)),
[all …]
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| /rk3399_ARM-atf/plat/mediatek/mt8192/drivers/spm/ |
| H A D | mt_spm_cond.c | 77 #define IDLE_CG(mask, addr, bitflip, clkmux) \ macro
81 IDLE_CG(0xffffffff, SPM_PWR_STATUS, false, 0U),
82 IDLE_CG(0x00000200, INFRA_SW_CG0, true, 0U),
83 IDLE_CG(0x00000200, INFRA_SW_CG1, true, 0U),
84 IDLE_CG(0x00000200, INFRA_SW_CG2, true, 0U),
85 IDLE_CG(0x00000200, INFRA_SW_CG3, true, 0U),
86 IDLE_CG(0x00000200, INFRA_SW_CG4, true, 0U),
87 IDLE_CG(0x00000200, INFRA_SW_CG5, true, 0U),
88 IDLE_CG(0x00100000, MMSYS_CG_CON0, true, (CLK_CHECK | CLKMUX_DISP)),
89 IDLE_CG(0x00100000, MMSYS_CG_CON1, true, (CLK_CHECK | CLKMUX_DISP)),
[all …]
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