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Searched refs:GPIO0_BASE (Results 1 – 15 of 15) sorted by relevance

/rk3399_ARM-atf/plat/hisilicon/hikey/include/
H A Dhi6220.h56 #define GPIO0_BASE 0xF8011000 macro
/rk3399_ARM-atf/plat/rockchip/rk3568/
H A Drk3568_def.h47 #define GPIO0_BASE 0xfdd60000 macro
/rk3399_ARM-atf/plat/rockchip/rk3328/
H A Drk3328_def.h39 #define GPIO0_BASE 0xff210000 macro
/rk3399_ARM-atf/plat/rockchip/px30/
H A Dpx30_def.h34 #define GPIO0_BASE 0xff040000 macro
/rk3399_ARM-atf/plat/rockchip/rk3399/include/shared/
H A Daddressmap_shared.h35 #define GPIO0_BASE (MMIO_BASE + 0x07720000) macro
/rk3399_ARM-atf/plat/rockchip/rk3588/
H A Drk3588_def.h83 #define GPIO0_BASE 0xfd8a0000 macro
/rk3399_ARM-atf/plat/rockchip/rk3576/
H A Drk3576_def.h75 #define GPIO0_BASE 0x27320000 macro
/rk3399_ARM-atf/plat/rockchip/rk3328/drivers/soc/
H A Dsoc.c32 MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
/rk3399_ARM-atf/plat/rockchip/px30/drivers/pmu/
H A Dpmu.c1015 val = mmio_read_32(GPIO0_BASE + SWPORTA_DDR); in rockchip_soc_system_off()
1017 mmio_write_32(GPIO0_BASE + SWPORTA_DDR, val); in rockchip_soc_system_off()
1020 val = mmio_read_32(GPIO0_BASE); in rockchip_soc_system_off()
1022 mmio_write_32(GPIO0_BASE, val); in rockchip_soc_system_off()
/rk3399_ARM-atf/plat/hisilicon/hikey960/
H A Dhikey960_bl_common.c447 pl061_gpio_register(GPIO0_BASE, 0); in hikey960_gpio_init()
/rk3399_ARM-atf/plat/hisilicon/hikey/
H A Dhikey_bl_common.c53 pl061_gpio_register(GPIO0_BASE, 0); in hikey_gpio_init()
/rk3399_ARM-atf/plat/hisilicon/hikey960/include/
H A Dhi3660.h243 #define GPIO0_BASE UL(0xE8A0B000) macro
/rk3399_ARM-atf/plat/rockchip/rk3399/drivers/gpio/
H A Drk3399_gpio.c81 .port_base = GPIO0_BASE,
/rk3399_ARM-atf/plat/rockchip/rk3576/drivers/pmu/
H A Dpmu.c996 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, in rockchip_soc_system_off()
1000 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, in rockchip_soc_system_off()
/rk3399_ARM-atf/plat/rockchip/rk3588/drivers/pmu/
H A Dpmu.c1358 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DDR_L, in rockchip_soc_system_off()
1362 mmio_write_32(GPIO0_BASE + GPIO_SWPORT_DR_L, in rockchip_soc_system_off()