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Searched refs:FIELD_PREP (Results 1 – 9 of 9) sorted by relevance

/rk3399_ARM-atf/plat/ti/k3low/board/am62lx-evm/
H A Dboard_config.c36 pad_conf |= (FIELD_PREP(PAD_PULLUPDOWN_MASK, 1) | FIELD_PREP(PAD_INPUTACTIVE_MASK, 1)); in board_init()
41 pad_conf |= FIELD_PREP(PAD_PULLUPDOWN_MASK, 1); in board_init()
47 pad_conf |= (FIELD_PREP(PAD_PULLUPDOWN_MASK, 1) | FIELD_PREP(PAD_INPUTACTIVE_MASK, 1)); in board_init()
52 pad_conf |= FIELD_PREP(PAD_PULLUPDOWN_MASK, 1); in board_init()
/rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/common/
H A Dcps_drv_lpddr4.h32 #ifndef FIELD_PREP
33 #define FIELD_PREP(_mask, _val) \ macro
45 (reg_value & ~(CPS_FLD_MASK(fld))) | FIELD_PREP(CPS_FLD_MASK(fld), value); \
/rk3399_ARM-atf/include/drivers/cadence/
H A Dcdns_nand.h20 #define FIELD_PREP(_mask, _val) \ macro
168 (FIELD_PREP(CNF_ECC_CORR_STR_MASK, CNF_ECC_CORR_STR)))
176 (FIELD_PREP(CNF_SECTOR_OFFSET_MASK, CNF_SECTOR_OFFSET)))
183 (FIELD_PREP(CNF_LAST_SECTOR_MASK, CNF_LAST_SECTOR_SIZE)))
290 (FIELD_PREP(RESYNC_IDLE_CNT_MASK, RESYNC_IDLE_CNT)) | \
291 (FIELD_PREP(RESYNC_HIGH_CNT_MASK, RESYNC_HIGH_CNT)))
322 (FIELD_PREP(CNF_MARKER_MASK, CNF_MARKER_VAL)))
/rk3399_ARM-atf/plat/ti/k3low/include/
H A Dam62l_psc_minimal.h31 #ifndef FIELD_PREP
32 #define FIELD_PREP(_mask, _val) \ macro
/rk3399_ARM-atf/plat/ti/k3low/common/
H A Dam62l_psc_minimal.c71 FIELD_PREP(PDCTL_NEXT_STATE_MASK, pd_state))); in set_main_psc_state()
76 FIELD_PREP(MDCTL_NEXT_STATE_MASK, md_state))); in set_main_psc_state()
/rk3399_ARM-atf/plat/intel/soc/common/drivers/ccu/
H A Dncore_ccu.c35 #define FIELD_PREP(_mask, _val) \ macro
679 mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | in flush_l3_dcache()
680 FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_TAG), in flush_l3_dcache()
694 mmio_write_32(FIELD_PREP(CCU_DMI0_DMIUSMCMCR_MNTOP, FLUSH_ALL_ENTRIES) | in flush_l3_dcache()
695 FIELD_PREP(CCU_DMI0_DMIUSMCMCR_ARRAY_ID, ARRAY_ID_DATA), in flush_l3_dcache()
/rk3399_ARM-atf/plat/ti/k3low/common/drivers/k3-ddrss/
H A Dam62l_ddrss.c119 set_val = (reg_val & ~PLL_HSDIV_RESET_MASK) | FIELD_PREP(PLL_HSDIV_RESET_MASK, 1); in set_ddr_pll_div()
124 set_val = (reg_val & ~PLL_HSDIV_DIV_MASK) | FIELD_PREP(PLL_HSDIV_DIV_MASK, div); in set_ddr_pll_div()
129 set_val = (reg_val & ~PLL_HSDIV_CLKOUT_MASK) | FIELD_PREP(PLL_HSDIV_CLKOUT_MASK, 1); in set_ddr_pll_div()
134 set_val = (reg_val & ~PLL_HSDIV_RESET_MASK) | FIELD_PREP(PLL_HSDIV_RESET_MASK, 0); in set_ddr_pll_div()
/rk3399_ARM-atf/plat/intel/soc/agilex5/include/
H A Dagilex5_iossm_mailbox.h23 #define FIELD_PREP(_mask, _val) \ macro
/rk3399_ARM-atf/plat/intel/soc/agilex5/soc/
H A Dagilex5_iossm_mailbox.c777 cmd_param_0 = FIELD_PREP(BIST_START_ADDR_SPACE_MASK, mem_exp); in inline_ecc_bist_mem_init()