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Searched refs:DIV_PLL4DIVP (Results 1 – 3 of 3) sorted by relevance

/rk3399_ARM-atf/include/dt-bindings/clock/
H A Dstm32mp13-clksrc.h47 #define DIV_PLL4DIVP 7 macro
H A Dstm32mp15-clksrc.h69 #define DIV_PLL4DIVP 7 macro
/rk3399_ARM-atf/drivers/st/clk/
H A Dclk-stm32mp13.c794 DIV_CFG(DIV_PLL4DIVP, RCC_PLL4CFGR2, 0, 7, 0, NULL, DIV_NO_BIT_RDY),
1895 STM32_COMPOSITE(_PLL4P, PLL4_P, _CK_PLL4, 0, GATE_PLL4_DIVP, DIV_PLL4DIVP),