Searched refs:DDRC_UMCTL2_MP_BASE (Results 1 – 2 of 2) sorted by relevance
99 #define DDRC_UMCTL2_MP_BASE 0x403C03F8U macro
120 mmio_write_32(DDRC_UMCTL2_MP_BASE + OFFSET_DDRC_PCTRL_0, ENABLE_AXI_PORT); in enable_axi_ports()122 mmio_write_32(DDRC_UMCTL2_MP_BASE + OFFSET_DDRC_PCTRL_1, ENABLE_AXI_PORT); in enable_axi_ports()124 mmio_write_32(DDRC_UMCTL2_MP_BASE + OFFSET_DDRC_PCTRL_2, ENABLE_AXI_PORT); in enable_axi_ports()