Searched refs:DDRC_BASE (Results 1 – 2 of 2) sorted by relevance
| /rk3399_ARM-atf/drivers/nxp/ddr/s32cc/ |
| H A D | ddr_utils.c | 70 mmio_write_32(DDRC_BASE + OFFSET_DDRC_DBG1, DBG1_DISABLE_DE_QUEUEING); in set_axi_parity()
73 mmio_setbits_32(DDRC_BASE + OFFSET_DDRC_RFSHCTL3, RFSHCTL3_DISABLE_AUTO_REFRESH); in set_axi_parity()
76 mmio_clrbits_32(DDRC_BASE + OFFSET_DDRC_PWRCTL, PWRCTL_POWER_DOWN_ENABLE_MASK); in set_axi_parity()
79 mmio_clrbits_32(DDRC_BASE + OFFSET_DDRC_PWRCTL, PWRCTL_SELF_REFRESH_ENABLE_MASK); in set_axi_parity()
85 mmio_clrbits_32(DDRC_BASE + OFFSET_DDRC_PWRCTL, PWRCTL_EN_DFI_DRAM_CLOCK_DIS_MASK); in set_axi_parity()
88 mmio_write_32(DDRC_BASE + OFFSET_DDRC_SWCTL, SWCTL_SWDONE_ENABLE); in set_axi_parity()
91 err = mmio_read_32_poll_timeout(DDRC_BASE + OFFSET_DDRC_SWSTAT, swstat_reg, in set_axi_parity()
100 mmio_clrbits_32(DDRC_BASE + OFFSET_DDRC_DFIMISC, DFIMISC_DFI_INIT_COMPLETE_EN_MASK); in set_axi_parity()
103 mmio_write_32(DDRC_BASE + OFFSET_DDRC_SWCTL, SWCTL_SWDONE_DONE); in set_axi_parity()
105 err = mmio_read_32_poll_timeout(DDRC_BASE + OFFSET_DDRC_SWSTAT, swstat_reg, in set_axi_parity()
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| /rk3399_ARM-atf/include/drivers/nxp/ddr/s32cc/ |
| H A D | ddr_utils.h | 25 #define DDRC_BASE 0x403C0000U macro
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