| /rk3399_ARM-atf/plat/intel/soc/common/ |
| H A D | socfpga_sip_svc.c | 1104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
1478 uint32_t random_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
1661 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
1709 uint32_t key_len = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5);
2093 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2104 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2117 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2223 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2229 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
2237 x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
[all …]
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| /rk3399_ARM-atf/services/std_svc/rmmd/ |
| H A D | rmmd_main.c | 257 SMC_GET_GP(handle, CTX_GPREG_X5), in rmmd_smc_forward()
314 uint64_t x5 = SMC_GET_GP(handle, CTX_GPREG_X5); in rmmd_rmi_handler()
506 ide_key_info.keyqw1 = SMC_GET_GP(handle, CTX_GPREG_X5); in rmmd_rmm_el3_handler()
518 ret = rmmd_el3_ide_key_set_go(x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5)); in rmmd_rmm_el3_handler()
521 ret = rmmd_el3_ide_key_set_stop(x1, x2, x3, x4, SMC_GET_GP(handle, CTX_GPREG_X5)); in rmmd_rmm_el3_handler()
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| /rk3399_ARM-atf/plat/rockchip/rk3399/ |
| H A D | plat_sip_calls.c | 70 x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in rockchip_plat_sip_handler()
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| /rk3399_ARM-atf/services/std_svc/spmd/ |
| H A D | spmd_main.c | 121 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); in spmd_build_spmc_message()
273 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); in spmd_secure_interrupt_handler()
779 SMC_GET_GP(handle, CTX_GPREG_X5), in spmd_smc_switch_state()
786 SMC_GET_GP(handle, CTX_GPREG_X5), in spmd_smc_switch_state()
804 SMC_GET_GP(handle, CTX_GPREG_X5), in spmd_smc_switch_state()
932 SMC_GET_GP(handle, CTX_GPREG_X5), in spmd_smc_handler()
1092 write_ctx_reg(gpregs, CTX_GPREG_X5, 0); in spmd_smc_handler()
1134 SMC_GET_GP(handle, CTX_GPREG_X5), in spmd_smc_handler()
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| H A D | spmd_logical_sp.c | 148 write_ctx_reg(gpregs, CTX_GPREG_X5, 0U); in spmd_build_direct_message_req()
163 retval->arg5 = read_ctx_reg(gpregs, CTX_GPREG_X5); in spmd_encode_ctx_to_ffa_value()
204 write_ctx_reg(gpregs, CTX_GPREG_X5, 0U); in spmd_build_ffa_info_get_regs()
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| /rk3399_ARM-atf/plat/nvidia/tegra/soc/t186/drivers/mce/ |
| H A D | mce.c | 187 arg4 = read_ctx_reg(gp_regs, CTX_GPREG_X5); in mce_command_handler()
195 write_ctx_reg(gp_regs, CTX_GPREG_X5, (0ULL)); in mce_command_handler()
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| /rk3399_ARM-atf/services/spd/opteed/ |
| H A D | opteed_main.c | 712 CTX_GPREG_X5, in opteed_smc_handler()
714 CTX_GPREG_X5)); in opteed_smc_handler()
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| /rk3399_ARM-atf/services/spd/tlkd/ |
| H A D | tlkd_main.c | 332 write_ctx_reg(gp_regs, CTX_GPREG_X5, (uint32_t)(x2 >> 32)); in tlkd_smc_handler()
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| /rk3399_ARM-atf/plat/qti/qtiseclib/src/ |
| H A D | qtiseclib_cb_interface.c | 155 qti_ns_ctx->x5 = read_ctx_reg(get_gpregs_ctx(ctx), CTX_GPREG_X5); in qtiseclib_cb_get_ns_ctx()
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| /rk3399_ARM-atf/include/arch/aarch64/ |
| H A D | smccc_helpers.h | 57 write_ctx_reg((get_gpregs_ctx(_h)), (CTX_GPREG_X5), (_x5)); \
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| /rk3399_ARM-atf/include/lib/el3_runtime/aarch64/ |
| H A D | context.h | 43 #define CTX_GPREG_X5 U(0x28) macro
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| /rk3399_ARM-atf/plat/qti/common/src/ |
| H A D | qti_syscall.c | 180 u_register_t x5 = read_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X5); in qti_sip_mem_assign()
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| /rk3399_ARM-atf/services/std_svc/spm/el3_spmc/ |
| H A D | spmc_main.c | 1184 info_get_flags = SMC_GET_GP(handle, CTX_GPREG_X5); in partition_info_get_handler()
1484 assert(SMC_GET_GP(handle, CTX_GPREG_X5) == 0UL); in ffa_spm_id_get_handler()
1631 registers[3] = (uint32_t)SMC_GET_GP(handle, CTX_GPREG_X5); in spmc_ffa_console_log()
1640 registers[3] = SMC_GET_GP(handle, CTX_GPREG_X5); in spmc_ffa_console_log()
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| /rk3399_ARM-atf/drivers/arm/ethosn/ |
| H A D | ethosn_smc.c | 551 SMC_GET_GP(handle, CTX_GPREG_X5), in ethosn_smc_handler()
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| /rk3399_ARM-atf/services/std_svc/sdei/ |
| H A D | sdei_main.c | 1014 x5 = SMC_GET_GP(ctx, CTX_GPREG_X5); in sdei_smc_handler()
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